Patents by Inventor James D. Strom
James D. Strom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10969422Abstract: An embodiment of the invention may include a method and structure for determining a failure in a guard ring of a chip. The method may include measuring a current frequency of oscillation of a crack check circuit located within a guard ring. The method may include comparing the frequency to a baseline frequency of oscillation of the crack check circuit. The current frequency and baseline frequency may be normalized using a set of bypass lines. The method may include determining there is a failure of the guard ring based on the difference between the normalized frequency of oscillation and the baseline normalized frequency of oscillation.Type: GrantFiled: May 16, 2018Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: Grant P. Kesselring, James D. Strom, Ann Chen Wu
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Patent number: 10644709Abstract: A differential charge pump circuit for use in a phase-locked loop (PLL) circuit is disclosed. The circuit includes a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The circuit controls a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node.Type: GrantFiled: June 17, 2019Date of Patent: May 5, 2020Assignee: International Business Machines CorporationInventors: James D. Strom, Grant P. Kesselring, Ann Chen Wu, Scott R. Trcka
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Publication number: 20190353697Abstract: An embodiment of the invention may include a method and structure for determining a failure in a guard ring of a chip. The method may include measuring a current frequency of oscillation of a crack check circuit located within a guard ring. The method may include comparing the frequency to a baseline frequency of oscillation of the crack check circuit. The current frequency and baseline frequency may be normalized using a set of bypass lines. The method may include determining there is a failure of the guard ring based on the difference between the normalized frequency of oscillation and the baseline normalized frequency of oscillation.Type: ApplicationFiled: May 16, 2018Publication date: November 21, 2019Inventors: Grant P. Kesselring, James D. Strom, Ann Chen Wu
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Publication number: 20190305782Abstract: A differential charge pump circuit for use in a phase-locked loop (PLL) circuit is disclosed. The circuit includes a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The circuit controls a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node.Type: ApplicationFiled: June 17, 2019Publication date: October 3, 2019Inventors: James D. STROM, Grant P. KESSELRING, Ann Chen WU, Scott R. TRCKA
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Patent number: 10361707Abstract: A system and apparatus relating to a differential charge pump circuit for use in a phase-locked loop (PLL) circuit. A differential charge pump circuit can include a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The nodes are inputs to one of the sense amplifiers. The differential charge pump circuit is configured to control a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node. The differential charge pump circuit can also include a transistor with a gate coupled to an output of a sense amplifier.Type: GrantFiled: November 29, 2017Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: James D. Strom, Grant P. Kesselring, Ann Chen Wu, Scott R. Trcka
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Patent number: 10326450Abstract: A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.Type: GrantFiled: June 8, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Andrew D. Davies, David M. Friend, Grant P. Kesselring, James D. Strom
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Publication number: 20190165795Abstract: A system and apparatus relating to a differential charge pump circuit for use in a phase-locked loop (PLL) circuit. A differential charge pump circuit can include a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The nodes are inputs to one of the sense amplifiers. The differential charge pump circuit is configured to control a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node. The differential charge pump circuit can also include a transistor with a gate coupled to an output of a sense amplifier.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Inventors: James D. STROM, Grant P. KESSELRING, Ann Chen WU, Scott R. TRCKA
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Patent number: 10250267Abstract: A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.Type: GrantFiled: December 15, 2017Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: David M. Friend, Grant P. Kesselring, James D. Strom, Alan P. Wagstaff
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Publication number: 20180358969Abstract: A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.Type: ApplicationFiled: June 8, 2017Publication date: December 13, 2018Inventors: Andrew D. Davies, David M. Friend, Grant P. Kesselring, James D. Strom
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Patent number: 10116260Abstract: A system includes a voltage controlled oscillator (VCO) having an adjustable amplitude. The amplitude of the VCO may be adjusted by adjusting voltage level present at a center tap node of an inductor. The VCO may have an adjustable amplitude that may be programmed on a chip-by-chip basis based on a chip parameter, power consumption, or oscillator performance.Type: GrantFiled: December 16, 2015Date of Patent: October 30, 2018Assignee: International Business Machines CorporationInventors: Andrew D. Davies, David M. Friend, Christopher W. Steffen, James D. Strom
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Publication number: 20180299503Abstract: The present disclosure discloses an IC with an electromigration (EM) monitor. The IC includes a functional circuit configured according to a first value of a parameter related to EM tolerance. The IC also includes a dummy version of the functional circuit configured according to a second value of the parameter. The second value causes the dummy version of the functional circuit to be more sensitive to an EM event than the functional circuit. Upon the EM monitor determines that the EM event occurs in the dummy version of the functional circuit, the EM monitor asserts a signal indicating that the EM event has occurred in the dummy version of the functional circuit and providing a warning that the EM event is likely to occur in the functional circuit.Type: ApplicationFiled: April 13, 2017Publication date: October 18, 2018Inventors: David M. FRIEND, Grant P. KESSELRING, Eric J. LUKES, James D. STROM
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Patent number: 10088519Abstract: The present disclosure discloses an IC with an electromigration (EM) monitor. The IC includes a functional circuit configured according to a first value of a parameter related to EM tolerance. The IC also includes a dummy version of the functional circuit configured according to a second value of the parameter. The second value causes the dummy version of the functional circuit to be more sensitive to an EM event than the functional circuit. Upon the EM monitor determines that the EM event occurs in the dummy version of the functional circuit, the EM monitor asserts a signal indicating that the EM event has occurred in the dummy version of the functional circuit and providing a warning that the EM event is likely to occur in the functional circuit.Type: GrantFiled: April 13, 2017Date of Patent: October 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Friend, Grant P. Kesselring, Eric J. Lukes, James D. Strom
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Publication number: 20180109265Abstract: A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.Type: ApplicationFiled: December 15, 2017Publication date: April 19, 2018Inventors: David M. Friend, Grant P. Kesselring, James D. Strom, Alan P. Wagstaff
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Patent number: 9929722Abstract: Embodiments herein describe a transmission line used to carry an AC signal (e.g., a high-speed clock signal) between two different voltage domains in an IC. Instead of dividing the transmission line into multiple segments each with a buffer, in one embodiment the transmission line is arranged to form a capacitor. That is, the conductive material forming the transmission line is arranged in the IC to result in a desired capacitance. This capacitance can be used to replace a discrete capacitor that would otherwise be used with a buffer (e.g., level shifter) located at the end of the transmission line for converting the AC signal from a first voltage domain to a second voltage domain.Type: GrantFiled: January 30, 2017Date of Patent: March 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Friend, Grant P. Kesselring, Christopher W. Steffen, James D. Strom
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Patent number: 9923565Abstract: A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.Type: GrantFiled: November 19, 2014Date of Patent: March 20, 2018Assignee: International Business Machines IncorporatedInventors: David M. Friend, Grant P. Kesselring, James D. Strom, Alan P. Wagstaff
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Patent number: 9882552Abstract: A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.Type: GrantFiled: September 25, 2015Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Friend, Grant P. Kesselring, Michael A. Sperling, James D. Strom
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Patent number: 9871527Abstract: A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.Type: GrantFiled: January 30, 2017Date of Patent: January 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Friend, Grant P. Kesselring, Michael A. Sperling, James D. Strom
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Publication number: 20170179884Abstract: A system includes a voltage controlled oscillator (VCO) having an adjustable amplitude. The amplitude of the VCO may be adjusted by adjusting voltage level present at a center tap node of an inductor. The VCO may have an adjustable amplitude that may be programmed on a chip-by-chip basis based on a chip parameter, power consumption, or oscillator performance.Type: ApplicationFiled: December 16, 2015Publication date: June 22, 2017Inventors: Andrew D. Davies, David M. Friend, Christopher W. Steffen, James D. Strom
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Publication number: 20170141781Abstract: A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Inventors: David M. FRIEND, Grant P. KESSELRING, Michael A. SPERLING, James D. STROM
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Publication number: 20170093383Abstract: A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: David M. FRIEND, Grant P. KESSELRING, Michael A. SPERLING, James D. STROM