Patents by Inventor James D. Yoder
James D. Yoder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8867182Abstract: The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.Type: GrantFiled: June 7, 2010Date of Patent: October 21, 2014Assignee: Agere Systems Inc.Inventors: Boris A. Bark, Brad L. Grande, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Publication number: 20140270122Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Applicant: Agere Systems LLCInventors: King-Hon Lau, Johannes G. Ransjin, Harold T. Simmonds, James D. Yoder
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Patent number: 8761236Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.Type: GrantFiled: April 12, 2012Date of Patent: June 24, 2014Assignee: Agere Systems LLCInventors: King-Hon Lau, Johannes G. Ransijn, Harold T. Simmonds, James D. Yoder
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Publication number: 20130251140Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: ApplicationFiled: May 10, 2013Publication date: September 26, 2013Applicant: Agere Systems LLCInventors: Johannes G. Ransijn, Boris A. Bark, James D. Yoder, Peter Kiss
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Patent number: 8442212Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: GrantFiled: April 28, 2011Date of Patent: May 14, 2013Assignee: Agere Systems LLCInventors: Johannes G. Ransijn, Boris A. Bark, James D. Yoder, Peter Kiss
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Publication number: 20120195354Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the EA rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.Type: ApplicationFiled: April 12, 2012Publication date: August 2, 2012Applicant: Agere Systems Inc.Inventors: King-Hon Lau, Johannes G. Ransijn, Harold T. Simmonds, James D. Yoder
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Patent number: 8213489Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.Type: GrantFiled: August 17, 2005Date of Patent: July 3, 2012Assignee: Agere Systems Inc.Inventors: King-Hon Lau, Johannes G. Ransijn, Harold Thomas Simmonds, James D Yoder
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Publication number: 20110222682Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: ApplicationFiled: April 28, 2011Publication date: September 15, 2011Applicant: AGERE SYSTEMS INC.Inventors: Johannes G. Ransijn, Boris A. Bark, James D. Yoder, Peter Kiss
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Patent number: 7969335Abstract: Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.Type: GrantFiled: March 3, 2008Date of Patent: June 28, 2011Assignee: Agere Systems Inc.Inventors: Jesus Arias, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Patent number: 7940921Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: GrantFiled: June 23, 2005Date of Patent: May 10, 2011Assignee: Agere Systems Inc.Inventors: Boris A. Bark, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Publication number: 20100246695Abstract: The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.Type: ApplicationFiled: June 7, 2010Publication date: September 30, 2010Applicant: AGERE SYSTEMS INC.Inventors: Boris A. Bark, Brad L. Grande, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Patent number: 7773733Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: GrantFiled: June 23, 2005Date of Patent: August 10, 2010Assignee: Agere Systems Inc.Inventors: Boris A. Bark, Brad L. Grande, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Publication number: 20080150773Abstract: Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.Type: ApplicationFiled: March 3, 2008Publication date: June 26, 2008Inventors: Jesus ARAIS, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Patent number: 7362247Abstract: Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.Type: GrantFiled: May 8, 2006Date of Patent: April 22, 2008Assignee: Agere Systems Inc.Inventors: Jesus Arias, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Patent number: 6552838Abstract: An electro-optic modulator and associated method are provided. The electro-optic modulator includes an optical waveguide comprised of two pairs of coplanar modulation strips, the strips being driven by a controller circuit which applies voltages of equal amplitude and opposite polarity to the strips of each pair. The voltage applied to the first pair of strips may differ from the voltage applied to the second pair of strips, so that a chirp factor may be adjusted if desired. The modulator and associated method exhibit reduced drive voltage requirements.Type: GrantFiled: July 18, 2001Date of Patent: April 22, 2003Assignee: Agere Systems Inc.Inventors: Johannes G. Ransijn, James D. Yoder
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Patent number: 6542008Abstract: A system and method are provided for providing an impedance match of an output buffer to a transmission line without significantly increasing the power consumption of the output buffer. A system and method are also provided for providing an impedance match of an output buffer to a transmission line, while still allowing for an adjustable output swing as is required for loads such as laser transmitters and optical modulators.Type: GrantFiled: November 28, 2000Date of Patent: April 1, 2003Assignee: Agere Systems Inc.Inventors: Dwight D. Daugherty, Johannes G. Ransijn, Gregory C. Salvador, James D. Yoder, Kenneth D. Gaynor
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Publication number: 20030016430Abstract: An electro-optic modulator and associated method are provided. The electro-optic modulator includes an optical waveguide comprised of two pairs of coplanar modulation strips, the strips being driven by a controller circuit which applies voltages of equal amplitude and opposite polarity to the strips of each pair. The voltage applied to the first pair of strips may differ from the voltage applied to the second pair of strips, so that a chirp factor may be adjusted if desired. The modulator and associated method exhibit reduced drive voltage requirements.Type: ApplicationFiled: July 18, 2001Publication date: January 23, 2003Inventors: Johannes G. Ransijn, James D. Yoder