Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.

Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.