Patents by Inventor James David Ingalls

James David Ingalls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9747996
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 29, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
  • Publication number: 20170140832
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
  • Publication number: 20170103818
    Abstract: Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.
    Type: Application
    Filed: July 11, 2016
    Publication date: April 13, 2017
    Inventors: Austin H. Roach, Matthew Gadlage, Adam Duncan, James David Ingalls, Matthew Kay
  • Patent number: 9620242
    Abstract: Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 11, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Austin H. Roach, Matthew Gadlage, Adam Duncan, James David Ingalls, Matthew Kay
  • Patent number: 9601214
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 21, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
  • Patent number: 9536620
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: January 3, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
  • Publication number: 20160284418
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
  • Publication number: 20160086676
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Application
    Filed: December 3, 2015
    Publication date: March 24, 2016
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
  • Patent number: 9263139
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 16, 2016
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
  • Publication number: 20150138887
    Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
    Type: Application
    Filed: September 30, 2014
    Publication date: May 21, 2015
    Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard