Abstract: A tool is provided that automates and expedites the ASIC design review process by allowing designers to perform a comprehensive asynchronous path design review of the circuit design HDL code. The tool operates on either an entire hierarchy or any sub-block of the circuit design. Filters are provided to allow the user to disregard known and desired synchronization circuits from the output generated by the tool. The tool provides an output that can take either of two formats, i.e. the output may be presented in a tabular form by hierarchical signal name, or it may be presented in a graphical, schematic block diagram form. In operation, the tool performs an exhaustive search of all circuits and identifies any asynchronous behavior. A user interface is provided that requires two data inputs and provides for an additional optional field. The two mandatory fields identify the location of all design files and the module at which the tool should begin its analysis.