Patents by Inventor James David Sawin
James David Sawin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9772948Abstract: A new segment of data is copied to a volatile, primary cache based on a host data read access request. The primary cache mirrors a first portion of a non-volatile main storage criterion is determined for movement of data from the primary cache to a non-volatile, secondary cache that mirrors a second portion of the main storage. The criterion gives higher priority to segments having addresses not yet selected for reading by the host. In response to the new segment of data being copied to the primary cache, a selected segment of data is copied from the primary cache to the secondary cache in response to the selected segment satisfying the criterion.Type: GrantFiled: July 6, 2012Date of Patent: September 26, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: James David Sawin, Luke W. Friendshuh, Sumanth Jannyavula Venkata, Ryan James Goss, Mark Allen Gaertner
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Patent number: 9594685Abstract: Host read operations affecting a first logical block address of a data storage device are tracked. The data storage device includes a main storage and a non-volatile cache that mirrors a portion of data of the main storage. One or more criteria associated with the host read operations are determined. The criteria are indicative of future read requests of second logical block address associated with the first logical block address. Data of the at least the second logical block address is copied from the main storage to the non-volatile cache if the criteria meets a threshold.Type: GrantFiled: July 6, 2012Date of Patent: March 14, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: James David Sawin, Luke W. Friendshuh, Sumanth Jannyavula Venkata, Ryan James Goss, Mark Allen Gaertner
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Patent number: 9529724Abstract: Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.Type: GrantFiled: July 6, 2012Date of Patent: December 27, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Sumanth Jannyavula Venkata, James David Sawin, Yunaldi Yulizar, Ryan James Goss
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Patent number: 9477591Abstract: Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses (LBAs) that correspond to a memory space of a primary memory. The host LBA range is mapped to clusters of secondary memory LBAs, the secondary memory LBAs corresponding to a memory space of a secondary memory. Each incoming memory access request queued in the set of incoming queues is transformed into one or more outgoing memory access requests that include a range of secondary memory LBAs or one or more clusters of secondary memory LBAs. The outgoing memory access requests are routed in a set of outgoing queues. The secondary memory is accessed using the outgoing memory access requests.Type: GrantFiled: July 6, 2012Date of Patent: October 25, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Sumanth Jannyavula Venkata, James David Sawin
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Patent number: 9104578Abstract: A host read request affects a request address range of a main storage. A speculative address range proximate to the request address range is defined. Speculative data stored in the speculative address range is not requested via the host read request. A criterion is determined that is indicative of future read requests of associated with the speculative data. The speculative data is copied from the main storage to at least one of a non-volatile cache and a volatile cache together with data of the host read request in response to the criterion meeting a threshold. The non-volatile cache and the volatile cache mirror respective portions of the main storage.Type: GrantFiled: July 6, 2012Date of Patent: August 11, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: James David Sawin, Luke William Friendshuh, Sumanth Jannyavula Venkata, Ryan James Goss, Mark Allen Gaertner
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Publication number: 20140013026Abstract: Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses (LBAs) that correspond to a memory space of a primary memory. The host LBA range is mapped to clusters of secondary memory LBAs, the secondary memory LBAs corresponding to a memory space of a secondary memory. Each incoming memory access request queued in the set of incoming queues is transformed into one or more outgoing memory access requests that include a range of secondary memory LBAs or one or more clusters of secondary memory LBAs. The outgoing memory access requests are routed in a set of outgoing queues. The secondary memory is accessed using the outgoing memory access requests.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: Sumanth Jannyavula Venkata, James David Sawin
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Publication number: 20140013053Abstract: A new segment of data is copied to a volatile, primary cache based on a host data read access request. The primary cache mirrors a first portion of a non-volatile main storage criterion is determined for movement of data from the primary cache to a non-volatile, secondary cache that mirrors a second portion of the main storage. The criterion gives higher priority to segments having addresses not yet selected for reading by the host. In response to the new segment of data being copied to the primary cache, a selected segment of data is copied from the primary cache to the secondary cache in response to the selected segment satisfying the criterion.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: James David Sawin, Luke W. Friendshuh, Sumanth Jannyavula Venkata, Ryan James Goss, Mark Allen Gaertner
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Publication number: 20140013027Abstract: Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: Sumanth Jannyavula Venkata, James David Sawin, Yunaldi Yulizar
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Publication number: 20140013052Abstract: Host read operations affecting a first logical block address of a data storage device are tracked. The data storage device includes a main storage and a non-volatile cache that mirrors a portion of data of the main storage. One or more criteria associated with the host read operations are determined. The criteria are indicative of future read requests of second logical block address associated with the first logical block address. Data of the at least the second logical block address is copied from the main storage to the non-volatile cache if the criteria meets a threshold.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: James David Sawin, Luke W. Friendshuh, Sumanth Jannyavula Venkata, Ryan James Goss, Mark Allen Gaertner
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Publication number: 20140013047Abstract: A host read request affects a request address range of a main storage. A speculative address range proximate to the request address range is defined. Speculative data stored in the speculative address range is not requested via the host read request. A criterion is determined that is indicative of future read requests of associated with the speculative data. The speculative data is copied from the main storage to at least one of a non-volatile cache and a volatile cache together with data of the host read request in response to the criterion meeting a threshold. The non-volatile cache and the volatile cache mirror respective portions of the main storage.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: James David Sawin, Luke W. Friendshuh, Samanth Jannyavula Venkata, Ryan James Goss, Mark Allen Gaertner