Patents by Inventor James David Sproch
James David Sproch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960346Abstract: One or more embodiments of a regulator circuit for providing power to a load device having a first power demand profile over time. The regulator circuit comprises a regulator and an energy storage device coupled to the regulator and the load device. The regulator circuit is configured to scavenge provided energy that is available beyond the first power demand profile. Further, the regulator circuit is configured to store that energy in the energy storage device, and the energy storage device is configured to augment deliverable peak power to the load device when the load device requires more power than is provided by the regulator circuit.Type: GrantFiled: October 8, 2020Date of Patent: April 16, 2024Assignee: GROQ, INC.Inventors: James David Sproch, Dinesh Maheshwari
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Publication number: 20240118922Abstract: A processor comprises a computational array of computational elements and an instruction dispatch circuit. The computational elements receive data operands via data lanes extending along a first dimension, and processes the operands based upon instructions received from the instruction dispatch circuit via instruction lanes extending along a second dimension. The instruction dispatch circuit receives raw instructions, and comprises an instruction dispatch unit (IDU) processor that processes a set of raw instructions to generate processed instructions for dispatch to the computational elements, where the number of processed instructions is not equal to the number of instructions of the set of raw instructions.Type: ApplicationFiled: December 20, 2023Publication date: April 11, 2024Inventors: Brian Lee Kurtz, Dinesh Maheshwari, James David Sproch
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Patent number: 9275182Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: March 31, 2015Date of Patent: March 1, 2016Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Publication number: 20150205904Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Applicant: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 9003348Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: February 24, 2014Date of Patent: April 7, 2015Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 8904336Abstract: A latch is analyzed to determine meta-stable voltage bias points, which are then used to determine one or more of a settling time of the latch, a mean time before failure (MTBF) for a synchronizing circuit using the latch, or a regeneration time constant (Tau). The latch is analyzed by decomposing the latch circuit into a feed-forward circuit and a feedback circuit and then determining a first transfer function for the feed-forward circuit and a second transfer function for the feedback circuit. The transfer functions are then used to solve for meta-stable voltage bias points. The meta-stable voltage bias points are used as an initial condition for a simulation or measurement of the latch in order to measure settling time. The voltage curve during the settling time of the latch is used to calculate a value for Tau.Type: GrantFiled: June 29, 2013Date of Patent: December 2, 2014Assignee: Synopsys, Inc.Inventors: John Henry Pasternak, James David Sproch
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Publication number: 20140173545Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: February 24, 2014Publication date: June 19, 2014Applicant: SYNOPSYS, INC.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 8661387Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: January 14, 2013Date of Patent: February 25, 2014Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Publication number: 20130132914Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: January 14, 2013Publication date: May 23, 2013Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 8362622Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: GrantFiled: April 24, 2009Date of Patent: January 29, 2013Assignee: Synopsys, Inc.Inventors: James David Sproch, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Publication number: 20100270597Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.Type: ApplicationFiled: April 24, 2009Publication date: October 28, 2010Applicant: SYNOPSYS, INC.Inventors: JAMES DAVID SPROCH, Victor Moroz, Xiaopeng Xu, Aditya Pradeep Karmarkar
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Patent number: 6038381Abstract: A computer-implemented process for determining a signal function for use in controlling the application of signal operands to a circuit-implemented function for the purpose of power reduction. The present invention receives a netlist represented as a graph data structure having nodes interconnected with signal lines. A node can have one output (single fan-out) or can have more than one output (multiple fan-outs). Termination points of the graph are identified as inputs to registers or primary outputs. From the termination points, and using a breadth-first traversal process, the present invention traverses each node of the netlist. A parent node is not processed in the breadth-first traversal until all of its child nodes have been processed. During traversal, an activation signal function is constructed for each input of a node. If the node has multiple outputs then a disjunctive Boolean expression is used, otherwise a conjunctive Boolean expression is used to determine the activation signal function.Type: GrantFiled: November 25, 1997Date of Patent: March 14, 2000Assignee: Synopsys, Inc.Inventors: Michael Munch, Bernd Wurth, Renu Mehra, James David Sproch