Patents by Inventor James David Strom
James David Strom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8686782Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: GrantFiled: November 30, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Patent number: 8373486Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: GrantFiled: March 27, 2012Date of Patent: February 12, 2013Assignee: International Business Machines CorporationInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Publication number: 20120187987Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: ApplicationFiled: March 27, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Publication number: 20120133413Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Patent number: 7760843Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: GrantFiled: August 7, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 7538625Abstract: A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.Type: GrantFiled: February 27, 2007Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: Michael David Cesky, James David Strom
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Publication number: 20080301503Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: ApplicationFiled: August 7, 2008Publication date: December 4, 2008Inventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 7453293Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: GrantFiled: August 29, 2006Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Publication number: 20080204154Abstract: A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.Type: ApplicationFiled: February 27, 2007Publication date: August 28, 2008Inventors: Michael David Cesky, James David Strom
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Publication number: 20080208541Abstract: A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL, and a design structure on which the subject circuit resides is provided. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.Type: ApplicationFiled: October 10, 2007Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael David Cesky, James David Strom
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Publication number: 20080116947Abstract: A method and apparatus for distributing charge pump current and voltage for phase-locked loop circuits includes a charge pump implemented with a plurality of charge pump stages, each providing substantially equal charge pump current. Each stage includes a respective associated buffer for receiving an incoming increment (INC) signal and an incoming decrement (DEC) signal and providing an output time delayed INC signal and an output time delayed DEC. A chain of the buffers is provided to pass the time delayed INC signals and the time delayed DEC signals to the respective charge pump stages. Each of the charge pump stages includes an enable input arranged for independently enabling each respective charge pump stage.Type: ApplicationFiled: November 20, 2006Publication date: May 22, 2008Inventors: Katherine Ellen Lobb, James David Strom
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Publication number: 20080116959Abstract: A method and apparatus for distributing charge pump current and voltage for phase-locked loop circuits, and a design structure on which the subject circuit resides are provided. A charge pump implemented with a plurality of charge pump stages, each providing substantially equal charge pump current. Each stage includes a respective associated buffer for receiving an incoming increment (INC) signal and an incoming decrement (DEC) signal and providing an output time delayed INC signal and an output time delayed DEC. A chain of the buffers is provided to pass the time delayed INC signals and the time delayed DEC signals to the respective charge pump stages. Each of the charge pump stages includes an enable input arranged for independently enabling each respective charge pump stage.Type: ApplicationFiled: October 15, 2007Publication date: May 22, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Katherine Ellen Hirsch, James David Strom
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Patent number: 7173482Abstract: A complementary metal oxide semiconductor (CMOS) voltage regulator for low headroom applications includes a differential input common mode range amplifier. The differential input common mode range amplifier is formed by a plurality of CMOS transistors. A source follower CMOS transistor is coupled to an output of the differential input common mode range amplifier for providing an output of the CMOS voltage regulator. A current source is coupled to the differential input common mode range amplifier for maintaining a bias current through the differential input common mode range amplifier.Type: GrantFiled: March 30, 2005Date of Patent: February 6, 2007Assignee: International Business Machines CorporationInventors: Katherine Ellen Lobb, Patrick Lee Rosno, James David Strom
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Patent number: 7118274Abstract: A method and a reference circuit for bias current switching are provided for implementing an integrated temperature sensor. A first bias current is generated and constantly applied to a thermal sensing diode. A second bias current is provided to the thermal sensing diode by selectively switching a multiplied current from a current multiplier to the thermal sensing diode or to a load diode. The reference circuit includes a reference current source coupled to current mirror. The current mirror provides a first bias current to a thermal sensing diode. The current mirror is coupled to a current multiplier that provides a multiplied current. A second bias current to the thermal sensing diode includes the first bias current and the multiplied current from the current multiplier. The second bias current to the thermal sensing diode is provided by selectively switching the multiplied current between the thermal sensing diode and a dummy load diode.Type: GrantFiled: May 20, 2004Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: Nghia Van Phan, Patrick Lee Rosno, James David Strom
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Patent number: 7119587Abstract: The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.Type: GrantFiled: May 20, 2004Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 7061284Abstract: The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled to the output of the third flip flop.Type: GrantFiled: May 20, 2004Date of Patent: June 13, 2006Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 6859092Abstract: A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.Type: GrantFiled: April 17, 2003Date of Patent: February 22, 2005Assignee: International Business Machines CorporationInventors: Eric John Lukes, Patrick Lee Rosno, James David Strom, Dana Marie Woeste
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Publication number: 20040207460Abstract: A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.Type: ApplicationFiled: April 17, 2003Publication date: October 21, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric John Lukes, Patrick Lee Rosno, James David Strom, Dana Marie Woeste
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Patent number: 6724256Abstract: A receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.Type: GrantFiled: November 7, 2002Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: James David Strom, Patrick Lee Rosno
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Patent number: 6693465Abstract: Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differential inputs will be pulled to a predetermined voltage. When the voltage on the differential inputs reach a reference voltage, an active device detects that the reference voltage has been reached, and produces a predetermined logic value on an output of the enhanced differential receiver. The enhanced differential receiver is not subject to oscillation when not actively driven. Delay through the enhanced differential receiver is not substantially greater than delay through a conventional differential receiver consisting of only a differential amplifier.Type: GrantFiled: January 16, 2003Date of Patent: February 17, 2004Assignee: International Business Machines CorporationInventors: Patrick Lee Rosno, James David Strom