Abstract: An example operation may include one or more of connecting, by a load leveler, to a blockchain network comprising a plurality of nodes and configured to store a common work item, computing, by the load leveler, loads across the plurality of the nodes that need to execute the common work item upon completion of current tasks, determining, by the load leveler, a network load impact based on execution of a common blockchain consensus checking process on the network nodes, executing, by the load leveler, a work assessment process based on the loads computed across the plurality of the nodes and on the determined network load impact of the blockchain network, and assigning, by the load leveler, new tasks to the nodes based on results of the execution of the work assessment process.

Abstract: A blockchain may be used as a stochastic timer. The posting of a blockchain solution for verification may be a trigger that determines an event schedule. Because the only entity that knows when the solution will be posted is the solving entity, the solving entity may be rewarded with the ability to potentially exploit this knowledge. However, because the solving of a blockchain is a competitive process, there is a risk that if the solving entity retains the solution for greater exploitation, then another entity will post the solution and therefore gain the benefit. A blockchain stochastic timer can thus provide the necessary incentive for entities to invest computational resources into blockchain solutions.

Abstract: An example operation may include one or more of connecting, by a load leveler, to a blockchain network comprising a plurality of nodes and configured to store a common work item, computing, by the load leveler, loads across the plurality of the nodes that need to execute the common work item upon completion of current tasks, determining, by the load leveler, a network load impact based on execution of a common blockchain consensus checking process on the network nodes, executing, by the load leveler, a work assessment process based on the loads computed across the plurality of the nodes and on the determined network load impact of the blockchain network, and assigning, by the load leveler, new tasks to the nodes based on results of the execution of the work assessment process.

Abstract: A blockchain may be used as a stochastic timer. The posting of a blockchain solution for verification may be a trigger that determines an event schedule. Because the only entity that knows when the solution will be posted is the solving entity, the solving entity may be rewarded with the ability to potentially exploit this knowledge. However, because the solving of a blockchain is a competitive process, there is a risk that if the solving entity retains the solution for greater exploitation, then another entity will post the solution and therefore gain the benefit. A blockchain stochastic timer can thus provide the necessary incentive for entities to invest computational resources into blockchain solutions.

Abstract: A heat treatment furnace, also referred to as a multi-chamber furnace, that includes a plurality of treatment chambers, each having heating and cooling dampers and being controllable to adjust a flow rate into the treatment chamber, the dampers of each treatment chamber being selectively and independently adjustable with respect to one another so as to allow simultaneous heat processing of a plurality of products in different treatment chambers at different respective heat treatment states depending on the amount of heating and cooling flow rates allowed to enter in each treatment chamber via the dampers.

Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Abstract: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Abstract: The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.

Abstract: Fail sites in a semiconductor are isolated through a difference image of a fail area and a healthy area. The fail area comprises an image of a semiconductor with a fail. The healthy area comprises an image of a semiconductor absent the fail or, in other words, an image of a semiconductor with healthy structure. Instructions cause a variation in the intensities of the difference image to appear at the fail site.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.