Abstract: A first signal conditioning circuit is formed from a first portion, a second portion and a third portion. Signal conditioning functions of each of these portions are facilitated by a predetermined type of integrated semiconductor die within which they are formed. Two different semiconductor dies are thus provided for facilitating integration of the first through third signal conditioning portions therein. Wire bonds are provided between the two different semiconductor dies in order to form circuit paths between the different first through third portions. The signal routing using between the two different semiconductor dies provides for completing of the first signal conditioning circuit having a first signal conditioning function. For example, circuits such as interstage matching circuits are disposed on a different semiconductor die than power amplifier circuits.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.