Patents by Inventor James Dinan

James Dinan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170090979
    Abstract: Technologies for integrated thread scheduling include a computing device having a network interface controller (NIC). The NIC is configured to detect and suspend a thread that is being blocked by one or more communication operations. A thread scheduling engine of the NIC is configured to move the suspended thread from a running queue of the system thread scheduler to a pending queue of the thread scheduling engine. The thread scheduling engine is further configured to move the suspended thread from the pending queue to a ready queue of the thread scheduling engine upon determining any dependencies and/or blocking communications operations have completed. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: James Dinan, Mario Flajslik, Tom St. John
  • Publication number: 20170094010
    Abstract: Technologies for communication with direct data placement include a number of computing nodes in communication over a network. Each computing node includes a many-core processor having an integrated host fabric interface (HFI) that maintains an association table (AT). In response to receiving a message from a remote device, the HFI determines whether the AT includes an entry associating one or more parameters of the message to a destination processor core. If so, the HFI causes a data transfer agent (DTA) of the destination core to receive the message data. The DTA may place the message data in a private cache of the destination core. Message parameters may include a destination process identifier or other network address and a virtual memory address range. The HFI may automatically update the AT based on communication operations generated by software executed by the processor cores. Other embodiments are described and claimed.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: James Dinan, Venkata Krishnan, Srinivas Sridharan, David A. Webb
  • Publication number: 20170093770
    Abstract: Technologies for filtering a received message include a receiving computing device to receive messages and a sender computing device to send messages. The receiving computing device is configured to retrieve a descriptor from a received message and retrieve another descriptor from an inspection entry of a network port entry selected from a network port entry table by the receiving computing device based on the logical network port that received the message. The receiving computing device is further configured to compare the descriptors to determine whether the descriptors match. Upon finding a match, the receiving computing device is still further configured to perform an operation corresponding to the inspection entries whose descriptor matches the descriptor of the message. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Mario Flajslik, James Dinan, Keith D. Underwood
  • Publication number: 20170093670
    Abstract: Technologies for monitoring communication performance of a high performance computing (HPC) network include a performance probing engine of a source endpoint node of the HPC network. The performance probing engine is configured to generate a probe request that includes a timestamp of the probe request and transmit the probe request to a destination endpoint node of the HPC network communicatively coupled to the source endpoint node via the HPC network. The performance probing engine is additionally configured to receive a probe response from the destination endpoint node via the HPC network and to generate another timestamp that corresponds to the probe request having been received. Further, the performance probing engine is configured to determine a round-trip latency as a function of the probe request and probe response timestamps. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: James Dinan, David Keppel
  • Publication number: 20170093731
    Abstract: Technologies for estimating network round-trip times include a sender computing node in network communication with a set of neighboring computing nodes. The sender computing node is configured to determine the set of neighboring computing nodes, as well as a plurality of subsets of the set of neighboring computing nodes. Accordingly, the sender computing node generates a message queue for each of the plurality of subsets, each message queue including a probe message for each neighboring node in the subset to which the message queue corresponds. The sender computing node is further configured to determine a round-trip time for each message queue (i.e., subset of neighboring computing nodes) based on a duration of time between the first probe message of the message queue being transmitted and an acknowledgment being received in response to the last probe message of the message queue being transmitted.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Mario Flajslik, James Dinan
  • Publication number: 20170085442
    Abstract: Technologies for aggregation-based message processing include multiple computing nodes in communication over a network. A computing node receives a message from a remote computing node, increments an event counter in response to receiving the message, determines whether an event trigger is satisfied in response to incrementing the counter, and writes a completion event to an event queue if the event trigger is satisfied. An application of the computing node monitors the event queue for the completion event. The application may be executed by a processor core of the computing node, and the other operations may be performed by a host fabric interface of the computing node. The computing node may be a target node and count one-sided messages received from an initiator node, or the computing node may be an initiator node and count acknowledgement messages received from a target node. Other embodiments are described and claimed.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: James Dinan, Mario Flajslik, David Keppel, Ulf R. Hanebutte
  • Publication number: 20170085625
    Abstract: Technologies for handling message passing interface receive operations include a compute node to determine a plurality of parameters of a receive entry to be posted and determine whether the plurality of parameters includes a wildcard entry. The compute node generates a hash based on at least one parameter of the plurality of parameters in response to determining that the plurality of parameters does not include the wildcard entry and appends the receive entry to a list in a bin of a posted receive data structure, wherein the bin is determined based on the generated hash. The compute node further tracks the wildcard entry in the posted receive data structure in response to determining the plurality of parameters includes the wildcard entry and appends the receive entry to a wildcard list of the posted receive data structure in response to tracking the wildcard entry.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Inventors: James Dinan, Mario Flajslik, Keith D. Underwood
  • Publication number: 20160381120
    Abstract: This disclosure is directed to a system for event dissemination. In general, a system may comprise a plurality of devices each including an event dissemination module (EDM) configured to disseminate events between the plurality of devices. New events may be generated during the normal course of operation in each of the plurality of devices. These events may be provided to at least one device designated as a network dispatch location. The network dispatch location may initiate the dissemination of the events. For example, each device may place received events into a local event queue within the device. The placement of an event into the local event queue may cause a counter in the EDM to increment. Incrementing the counter may, in turn, cause a trigger operation module in the EDM to perform at least one activity including, for example, forwarding the event to other devices within the plurality of devices.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: MARIO FLAJSLIK, JAMES DINAN, KEITH UNDERWOOD
  • Publication number: 20160314073
    Abstract: Technologies for one-side remote memory access communication include multiple computing nodes in communication over a network. A receiver computing node receives a message from a sender node and extracts a segment identifier from the message. The receiver computing node determines, based on the segment identifier, a segment start address associated with a partitioned global address space (PGAS) segment of its local memory. The receiver computing node may index a segment table stored in the local memory or in a host fabric interface. The receiver computing node determines a local destination address within the PGAS segment based on the segment start address and an offset included in the message. The receiver computing node performs a remote memory access operation at the local destination address. The receiver computing node may perform those operations in hardware by the host fabric interface of the receiver computing node. Other embodiments are described and claimed.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 27, 2016
    Inventors: James Dinan, Mario Flajslik
  • Publication number: 20160283295
    Abstract: Systems, apparatuses and methods may provide for detecting an outbound communication and identifying a context of the outbound communication. Additionally, a completion status of the outbound communication may be tracked relative to the context. In one example, tracking the completion status includes incrementing a sent messages counter associated with the context in response to the outbound communication, detecting an acknowledgement of the outbound communication based on a network response to the outbound communication, incrementing a received acknowledgements counter associated with the context in response to the acknowledgement, comparing the sent messages counter to the received acknowledgements counter, and triggering a per-context memory ordering operation if the sent messages counter and the received acknowledgements counter have matching values.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: Mario Flajslik, James Dinan
  • Publication number: 20160179587
    Abstract: A method comprising receiving control information at a first processing element from a second processing element, synchronizing objects within a shared global memory space of the first processing element with a shared global memory space of a second processing element in response to receiving the control information and generating a completion event indicating the first processing element has been synchronized with the second processing element.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Clement T. Cole, James Dinan, Gabriele Jost, Stanley C. Smith, Robert W. Wisniewski, Keith D. Underwood
  • Publication number: 20160100010
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a one-sided memory access to a PGAS in a distributed computing environment. The system may include a transceiver module configured to receive a message over a network, the message comprising a data portion and a data size indicator and an offset handler module configured to calculate a destination address from a base address of a memory buffer and an offset counter. The transceiver module may further be configured to write the data portion to the memory buffer at the destination address; and the offset handler module may further be configured to update the offset counter based on the data size indicator.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 7, 2016
    Applicant: Intel Corporation
    Inventors: Mario Flajslik, James Dinan
  • Publication number: 20160072908
    Abstract: Technologies for proxy-based multithreaded message passing include a number of computing nodes in communication over a network. Each computing node establishes a number of message passing interface (MPI) endpoints associated with threads executed within a host processes. The threads generate MPI operations that are forwarded to a number of proxy processes. Each proxy process performs the MPI operation using an instance of a system MPI library. The threads may communicate with the proxy processes using a shared-memory communication method. Each thread may be assigned to a particular proxy process. Each proxy process may be assigned dedicated networking resources. MPI operations may include sending or receiving a message, collective operations, and one-sided operations. Other embodiments are described and claimed.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 10, 2016
    Inventors: James Dinan, Srinivas Sridharan