Abstract: In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.

Abstract: A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.

Abstract: The present invention provides a cyclic redundancy check (CRC) calculation system for a packet arriving on an n-byte wide bus. In one embodiment, the system includes a bus-wide CRC subsystem configured to calculate an intermediate CRC value based on complete segments of the packet. In addition, the system includes a byte-wide CRC subsystem, coupled to the bus-wide subsystem, configured to calculate a remaining CRC value based on the intermediate CRC value and one or more bytes within an incomplete segment of the packet on a byte by byte basis. In addition, a method of calculating a CRC value for a packet arriving on a n-byte wide bus and a data transmission system incorporating the system are also disclosed.

Abstract: The present invention provides a cyclic redundancy check (CRC) calculation system for a packet arriving on an n-byte wide bus. In one embodiment, the system includes a bus-wide CRC subsystem configured to calculate an intermediate CRC value based on complete segments of the packet. In addition, the system includes a byte-wide CRC subsystem, coupled to the bus-wide subsystem, configured to calculate a remaining CRC value based on the intermediate CRC value and one or more bytes within an incomplete segment of the packet on a byte by byte basis. In addition, a method of calculating a CRC value for a packet arriving on a n-byte wide bus and a data transmission system incorporating the system are also disclosed.