Patents by Inventor James Doubler

James Doubler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8138790
    Abstract: In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: March 20, 2012
    Assignee: Lattice Semiconductor Corporation
    Inventors: James Doubler, Michael Hammer, Jin Zhang
  • Patent number: 7924054
    Abstract: A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: April 12, 2011
    Assignee: Lattice Semiconductor Corporation
    Inventors: James Doubler, Michael Hammer, Jin Zhang