Patents by Inventor James Drake

James Drake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160228189
    Abstract: A modular reconfigurable surgical robot for use in association with a surgical tool is disclosed. The surgical robot includes a linear module for linear movement; a turret module for rotational movement, and elbow roll module for rotational movement, and a wrist tilt module for rotational movement. The turret module has a turret rotational axis. The elbow roll module for rotational has an elbow roll rotational axis at an angle to the turret rotational axis. The wrist tilt module has a wrist tilt rotational axis at an angle to the turret rotational axis and the elbow roll rotational axis. The linear module, turret module, elbow roll module and wrist tilt module are operably connectable together to form the surgical robot and one of the modules is operably connectable to the surgical tool. The surgical robot may include an arch device unit attachable to one of the other modules.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 11, 2016
    Inventors: Andrew A. GOLDENBERG, Yi YANG, Liang MA, Joao Guilherme AMARAL, James DRAKE, Thomas LOOI
  • Patent number: 9369119
    Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Publication number: 20160157703
    Abstract: The present disclosure provides a tissue gripping device. The device comprises a head with contact face attachable to the distal end of at least one hollow member. The contact face has one or more openings in flow communication with a suction device though the at least one hollow member wherein a negative pressure gradient can be applied across the one or more openings to allow the head to grasp tissue. The device may comprise flexible members to facilitate the navigation of internal organs. Additionally, the head can have one or more tool holes. The tool hole can house an ejecting surgical clip for medical procedure. The device may further be attachable to a sensor or another medical device. The grasping allows fixation and manipulation of tissue, traversal of the small intestine, and counter traction for tool insertion.
    Type: Application
    Filed: June 18, 2014
    Publication date: June 9, 2016
    Inventors: Robert Brooks, Thomas Looi, James Drake
  • Publication number: 20160132096
    Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 12, 2016
    Inventors: Malcolm S. ALLEN-WARE, Alan James DRAKE, Michael Stephen FLOYD, Charles Robert LEFURGY, Karthick RAJAMANI, Tobias WEBEL
  • Patent number: 9251913
    Abstract: A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: February 2, 2016
  • Patent number: 9201879
    Abstract: A method of generating a feature vector for an image is disclosed. Values are determined from a plurality of points in a region of the image, each of the values being determined using at least two of the plurality of points. A periodic sequence of the determined values is determined based on an order of the plurality of points. The periodic sequence is phase variant to a starting point of the ordered plurality of points, the order of the plurality of points being determined according to a predetermined rule. The feature vector for one of the points is generated from a frequency domain representation of the periodic sequence, the feature vector being invariant to rotation with respect to the plurality of points.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: December 1, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Barry James Drake
  • Patent number: 9177388
    Abstract: A method of determining a hash code representing a portion of an image, is disclosed. A Delaunay region (e.g., 450) enclosing an image feature point (e.g., 210) representing at least the portion of the image is determined. The Delaunay region is determined from A* lattice points. A mapping transforming the Delaunay region to a predetermined canonical form is determined A point of the Delaunay region is received. The received point defines a plane containing the A* lattice points of the Delaunay region excluding the received point. A normal of the plane is determined by setting at least two co-ordinates of the normal to predetermined non-zero values, the two co-ordinates being selected according to the determined mapping. The hash code representing a portion of the image is determined according to a distance determined using the normal.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: November 3, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Alan Valev Tonisson, Barry James Drake, Scott Alexander Rudkin
  • Publication number: 20150109043
    Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Patent number: 8941426
    Abstract: A critical path monitor (CPM) is configured in an integrated circuit (IC). The IC includes a set of critical paths. The CPM includes a set of split paths, a split path in the set of split paths corresponding to a critical path in the set of critical paths, and a split path in the set of split paths including an edge detector. The edge detector is configured with a set of edge detector latches. A set of set-reset (SR) latches is configured such that an edge detector latch is associated with a corresponding SR latch. A reset signal is configured to reach the set of edge detector latches in an offset synchronization with a latch clock signal used in the set of edge detector latches. The CPM is configured to operate using a frequency of the latch clock signal such that the frequency is higher than a threshold frequency.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan James Drake, Michael Stephen Floyd, Pawel Owczarczyk, Gregory Scott Still, Marshall Dale Tiner, Xiaobin Yuan
  • Patent number: 8819733
    Abstract: An assistance method for selecting a program using a display device (112) is disclosed. The method (1200) selects one or more attributes associated with a first program, the one or more attributes being selected dynamically by a processor associated with the display device (112) according to one or more predetermined criteria. The method searches for a second program associated with one or more of the selected attributes. The second program and the one or more attributes associated therewith are displayed on the display device, according to the search for the second program.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 26, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Laurence Crew, Eileen Oi-Yan Mak, Jeonren Vendrig, Ernest Yiu Cheong Wan, Barry James Drake
  • Patent number: 8818113
    Abstract: Disclosed is a method of determining one or more event subsets within a plurality of images. Each image is associated with time and location data specifying the time and location of capture of the image. The method determines a time variable for each adjacent pair of images in a capture time ordered list of the plurality of images. A distance variable for each adjacent pair of images in the ordered list of images is then determined. The method determines speed data of the image capture device at the time and location of capture of each image. The ordered list of images is then partitioned into one or more event subsets on the basis of a cost function, the cost function being determined in accordance with a normalization of the time variable and distance variable, wherein the time variable and the distance variable are weighted relative to the speed data.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: August 26, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: David John Maunder, Rob Sangster, Barry James Drake
  • Publication number: 20140236963
    Abstract: “A system and method for linking a hash code to a portion of an image. A plurality of lattice points is selected in a multidimensional lattice to form a smallest enclosing region about a feature vector representing the portion of the image and a lattice point is determined from the selected plurality of lattice points according to a distribution criteria. The determined lattice point is common to the smallest enclosing region and a region of the lattice adjacent to the smallest enclosing region located within a query radius distance of the feature vector. When the feature vector is located within the query radius of a query vector the feature vector is considered a match. The method assigns the feature vector to the determined lattice point and stores a link between a hash code associated with the determined lattice point and the portion of the image.
    Type: Application
    Filed: September 25, 2012
    Publication date: August 21, 2014
    Inventors: Barry James Drake, Alan Valev Tonisson, Scott Alexander Rudkin
  • Publication number: 20140169681
    Abstract: A method of generating a feature vector for an image is disclosed. Values are determined from a plurality of points in a region of the image, each of the values being determined using at least two of the plurality of points. A periodic sequence of the determined values is determined based on an order of the plurality of points. The periodic sequence is phase variant to a starting point of the ordered plurality of points, the order of the plurality of points being determined according to a predetermined rule. The feature vector for one of the points is generated from a frequency domain representation of the periodic sequence, the feature vector being invariant to rotation with respect to the plurality of points.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 19, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: BARRY JAMES DRAKE
  • Publication number: 20130279806
    Abstract: A method of determining a hash code representing a portion of an image, is disclosed. A Delaunay region (e.g., 450) enclosing an image feature point (e.g., 210) representing at least the portion of the image is determined. The Delaunay region is determined from A* lattice points. A mapping transforming the Delaunay region to a predetermined canonical form is determined A point of the Delaunay region is received. The received point defines a plane containing the A* lattice points of the Delaunay region excluding the received point. A normal of the plane is determined by setting at least two co-ordinates of the normal to predetermined non-zero values, the two co-ordinates being selected according to the determined mapping. The hash code representing a portion of the image is determined according to a distance determined using the normal.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 24, 2013
    Inventors: ALAN VALEV TONISSON, BARRY JAMES DRAKE, SCOTT ALEXANDER RUDKIN
  • Patent number: 8543959
    Abstract: A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: September 24, 2013
  • Publication number: 20120313647
    Abstract: A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
  • Publication number: 20120301039
    Abstract: Disclosed is a method of determining one or more event subsets within a plurality of images. Each image is associated with time and location data specifying the time and location of capture of the image. The method determines a time variable for each adjacent pair of images in a capture time ordered list of the plurality of images. A distance variable for each adjacent pair of images in the ordered list of images is then determined. The method determines speed data of the image capture device at the time and location of capture of each image. The ordered list of images is then partitioned into one or more event subsets on the basis of a cost function, the cost function being determined in accordance with a normalisation of the time variable and distance variable, wherein the time variable and the distance variable are weighted relative to the speed data.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: David John Maunder, Rob Sangster, Barry James Drake
  • Publication number: 20120264632
    Abstract: The claimed invention provides for new sample preparation methods enabling direct sequencing of PCR products using pyrophosphate sequencing techniques. The PCR products may be specific regions of a genome. The techniques provided in this disclosure allows for SNP (single nucleotide polymorphism) detection, classification, and assessment of individual allelic polymorphisms in one individual or a population of individuals. The results may be used for diagnostic and treatment of patients as well as assessment of viral and bacterial population identification.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 18, 2012
    Inventors: John Harris Leamon, William Lun Lee, Jan Fredrik Simons, Brian Desany, Michael Todd Ronan, James Drake, Kenton Lohman, Michael Egholm, Jonathan Rothberg
  • Publication number: 20120266125
    Abstract: A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 18, 2012
  • Publication number: 20120266192
    Abstract: An assistance method for selecting a program using a display device (112) is disclosed. The method (1200) selects one or more attributes associated with a first program, the one or more attributes being selected dynamically by a processor associated with the display device (112) according to one or more predetermined criteria. The method searches for a second program associated with one or more of the selected attributes. The second program and the one or more attributes associated therewith are displayed on the display device, according to the search for the second program.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: LAURENCE CREW, EILEEN OI-YAN MAK, JEONREN VENDRIG, ERNEST YIU CHEONG WAN, BARRY JAMES DRAKE