Abstract: A system for booting a processor from NAND flash, comprising a NAND agnostic boot controller and a NAND flash device, wherein the NAND flash device further comprises a boot wrapper storing boot code in a predetermined format.

Abstract: In a digital data processing system having a memory component, a structure and method for managing available memory resources. Free pointers to respective free memory blocks are stored in memory blocks maintained as a linked list. In a system having a hierarchically-organized memory component, a small number of the free pointers are maintained at a relatively higher performance level of the memory and the balance of the free pointers are maintained at a relatively lower performance level of the memory.

Abstract: In a memory controller for use with a DDR SDRAM, an apparatus improves the immunity of the controller to noise glitches on the DQS signal provided by the DDR SDRAM during READ operations. A method adjusts the noise immunity provided by the apparatus. In particular DQS quality circuits frame the DQS signal for a predetermined portion of the READ operation.

Abstract: In a digital data processing system having a memory component, a structure and method for managing available memory resources. Free pointers to respective free memory blocks are stored in memory blocks maintained as a linked list. In a system having a hierarchically-organized memory component, a small number of the free pointers are maintained at a relatively higher performance level of the memory and the balance of the free pointers are maintained at a relatively lower performance level of the memory.

Abstract: In a memory controller for use with a DDR SDRAM, apparatus for improving the immunity of the controller to noise glitches on the DQS signal provided by the DDR SDRAM during READ operations. A method is also disclosed for adjusting the noise immunity provided by the disclosed apparatus.

Abstract: A direct memory access controller is provided which utilizes a single dedicated controller to control all or substantially all memory accesses in a computer system, both memory-to-memory accesses within the system and transfers between system memory and various system peripherals. At least portions of the controller are time shared by various channels, each channel performing data transfers in a selected direction between a system memory component and a second component which may be a peripheral, another memory component or the like. An arbiter is provided as part of the controller for determining the channel using shared resources at any given time. Where one of the peripherals is a variable length packetized data source, multiple subchannels may be provided for transfers of data for such source into system memory, each such subehannel being for transfers to buffers of different size.