Abstract: An in-circuit test probe apparatus for probing the finely and closely spaced leads of an LSI circuit package in order to monitor the signals on the pins. A magnetic holding assembly is utilized to attach the test probe apparatus to the circuit package which is positioned with a cavity in the bottom of the test probe apparatus. A layer of silicon rubber is positioned between rough and fine probe pin location members to hold the probes during test and to allow easy insertion and removal of the test probe.

Abstract: An improved circuit for detection of horizontal sync pulses for use in high esolution digital processing of video data when low line-to-line registration uncertainty is required. The detector comprises three main parts, a negative peak detector, a proportioning amplifier and a high speed comparator for level detection. The peak detector allows a reference point to be established over a wide signal and temperature range with little error due to inherent accuracy and stability of the operational amplifier circuitry, and has an ability to adjust the triggering point of a comparator dependent upon video signal level.

Abstract: A bicycle storage structure which includes an elongated housing with one closed end and an opening at the other end. The housing has a top and a bottom joined by spaced side panels with one or more laterally projecting members protruding from the side panels into the interior of the housing. Said members having a surface adapted to overlie the pedals of a bicycle within the housing and prevent turning of the pedals as the bicycle is withdrawn from the housing.

Abstract: A power supply sequencing apparatus utilizing a pair of MOS-FET devices to simultaneously apply or remove the positive and negative power supply sources to an electronic unit.

Abstract: A bucket brigade A/D weighting function multiplier which provides a simultaneous A/D conversion and multiplication by a weighting function in a continuous pipe line fashion, is disclosed. Each converted bit from the A/D converter is utilized by the multiplier as it becomes available instead of waiting for the conversion of the entire word, to provide a weighted digital output.

Abstract: A digital-to-analog converter is described in which a first circuit including charge storage means provides charge packets corresponding to digitally weighted samples of an analog reference voltage. A predetermined pattern of digital signals cooperates with gating means to determine which charge storage devices in a second circuit will be charged with the charge packets stored in the first circuit. In one embodiment, the selected charges stored in the second circuit are shifted serially, accumulated, and sensed to provide an analog output signal. In another embodiment, the selected charges stored in the second circuit are accumulated and sensed.

Abstract: A bucket brigade analog-to-digital converter, which is a charge coupled analog-to-digital device that is made up of successive stages with each stage in one aspect including potential wells, and in another aspect including capacitors is disclosed. The charge or portion thereof in each stage is passed on to each successive stage in response to clock pulses, and compared in each stage with a different predetermined reference charge or voltage. The comparator output of each stage constitutes one bit of digital data.

Abstract: A D/A conversion circuit has each branch of its resistive binary scaling network energized by a switchable network. Each switchable network employs the internal current paths of an Integrated Circuit (I.C.) solid state device, such as a Complementary-Metal-Oxide Semiconductor-Field-Effect-Transistor (CMOSFET) device, which provides complementary switching action. Each switchable network also employs a Metal-Silicon (M-S) diode, which provides clamping and diode switching actions. By a combination of I.C. device and M-S diode device actions, the following features are achieved in a single circuit: (A) high accuracies, (B) fast setting times and (C) low power consumption. Also disclosed is a cooperating variable D/A reference potential source which achieves temperature compensation.