Patents by Inventor James E. Burnette
James E. Burnette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932979Abstract: A laundry treating appliance for treating laundry items according to an automatic cycle of operation can include a cabinet defining an interior and having an access opening providing access to the interior. A tub can be located within the interior and can at least partially define a liquid chamber. A drum is rotatably mounted within the liquid chamber and at least partially defines a treating chamber. A clothes mover is located within the treating chamber and rotatable about a vertical axis. The clothes mover can include a base and a barrel.Type: GrantFiled: September 2, 2020Date of Patent: March 19, 2024Assignee: WHIRLPOOL CORPORATIONInventors: Jonathan A. Andrejczuk, Adam Gary, Philip J. Czarnecki, Benjamin D. Lowell, Sayer J. Murphy, James Jeffery, Eric W. Merrow, Emmanuel F. Gonzaga, Thomas R. Scott, Donald E. Erickson, Bradley D. Morrow, Jason S. Burnette, Kevin Peralta, Corinne M. Gorenchan, Kenneth L. McConnell
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Patent number: 9389635Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.Type: GrantFiled: November 9, 2015Date of Patent: July 12, 2016Assignee: Apple Inc.Inventors: Greg M. Hess, James E. Burnette, II
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Publication number: 20160062388Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.Type: ApplicationFiled: November 9, 2015Publication date: March 3, 2016Inventors: Greg M. Hess, James E. Burnette, II
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Patent number: 9230690Abstract: Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.Type: GrantFiled: November 7, 2012Date of Patent: January 5, 2016Assignee: Apple Inc.Inventors: Greg M Hess, James E Burnette, II
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Patent number: 9207705Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.Type: GrantFiled: November 7, 2012Date of Patent: December 8, 2015Assignee: Apple Inc.Inventors: Greg M Hess, James E Burnette, II
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Patent number: 8988957Abstract: A sense amplifier test circuit that may allow for detecting soft failures may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier.Type: GrantFiled: November 7, 2012Date of Patent: March 24, 2015Assignee: Apple Inc.Inventors: Greg M Hess, James E Burnette, II
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Patent number: 8912853Abstract: A dynamic level shifter circuit and a ring oscillator implemented using the same are disclosed. A dynamic level shifter may include a pull-down circuit and a pull-up circuit. The pull-up circuit may include an extra transistor configured to reduce the current through that circuit when the pull-down circuit is activated. A ring oscillator may be implemented using instances of the dynamic level shifter along with instances of a static level shifter. The ring oscillator may also include a pulse generator configured to initiate oscillation. The ring oscillator implemented with dynamic level shifters may be used in conjunction with another ring oscillator implemented using only static level shifters to compare relative performance levels of the static and dynamic level shifters.Type: GrantFiled: June 14, 2012Date of Patent: December 16, 2014Assignee: Apple Inc.Inventors: James E. Burnette, Greg M. Hess, Shinye Shiu
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Publication number: 20140129884Abstract: Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: APPLE INC.Inventors: Greg M. Hess, James E. Burnette, II
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Publication number: 20140126312Abstract: Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: APPLE INC.Inventors: Greg M. Hess, James E. Burnette, II
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Publication number: 20140129868Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: APPLE INC.Inventors: Greg M Hess, James E Burnette, II
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Publication number: 20130335152Abstract: A dynamic level shifter circuit and a ring oscillator implemented using the same are disclosed. A dynamic level shifter may include a pull-down circuit and a pull-up circuit. The pull-up circuit may include an extra transistor configured to reduce the current through that circuit when the pull-down circuit is activated. A ring oscillator may be implemented using instances of the dynamic level shifter along with instances of a static level shifter. The ring oscillator may also include a pulse generator configured to initiate oscillation. The ring oscillator implemented with dynamic level shifters may be used in conjunction with another ring oscillator implemented using only static level shifters to compare relative performance levels of the static and dynamic level shifters.Type: ApplicationFiled: June 14, 2012Publication date: December 19, 2013Inventors: James E. Burnette, Greg M. Hess, Shinye Shiu
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Patent number: 8558603Abstract: A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter.Type: GrantFiled: December 15, 2011Date of Patent: October 15, 2013Assignee: Apple Inc.Inventors: Greg M. Hess, Naveen Javarappa, James E. Burnette, II
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Publication number: 20130154712Abstract: A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Inventors: Greg M. Hess, Naveen Javarappa, James E. Burnette, II
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Patent number: 8397199Abstract: In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).Type: GrantFiled: April 19, 2010Date of Patent: March 12, 2013Assignee: Apple Inc.Inventors: Apurva H. Soni, Antonietta Oliva, Edgardo F. Klass, Matthew J. T. Page, James E. Burnette, II
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Publication number: 20110257954Abstract: In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).Type: ApplicationFiled: April 19, 2010Publication date: October 20, 2011Inventors: Apurva H. Soni, Anonietta Oliva, Edgardo F. Klass, Matthew J.T. Page, James E. Burnette, II
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Patent number: 5182419Abstract: A saboted projectile comprises a sub-caliber, spin-stabilized warhead (usually an armor-piercing penetrator) and a full caliber spin-stabilized non-disintegrating sabot capable of being fired by airplanes. The sabot releasably receives the armor-piercing penetrator and is adapted to be mounted on a conventional ammunition cartridge. The sabot includes a novel method of holding the penetrator until firing, tightening a reverse threaded end cap against the aft end of the penetrator during firing and utilizing interior end cap geometry to utilize firing gas pressure to accelerate the penetrator forward in relation to the sabot after leaving the gun barrel. Accuracy is increased by maintaining axial symmetry and releasing the penetrator in substantially the same way each time. There are other novel features.Type: GrantFiled: February 19, 1986Date of Patent: January 26, 1993Assignee: ASI Systems InternationalInventor: James E. Burnette