Abstract: A system for providing model level protection for resources holding data accessed by multiple tasks in a model is discussed. The protection occurs at the model level so that the protection mechanism does not interfere with model dynamics. Resources concurrently accessed by multiple tasks are identified so that a unified protection mechanism can be applied to the resource. A user interface may be provided which enables the selection of a particular type of protection mechanism for the data in the resource. User supplied protection mechanisms may also be implemented.

Abstract: An embodiment can include one or more computer readable media storing executable instructions for performing execution scheduling for code generated from an executable graphical model. The media can store instructions for accessing a first code portion having a first priority, and a second code portion having a second priority, where the second priority has a relationship with the first priority. The media can store instructions for accessing target environment characteristics that indicate a performance of the target environment, and for performing execution scheduling for the first code portion and the second code portion, the execution scheduling taking into account the target environment characteristics, the execution scheduling using an execution schedule.

Abstract: When executing a graphical model of a dynamic system that includes two or more concurrently executing sets of operations, a processor is configured to create a first buffer and a second buffer within the executable graphical model. A first set of operations is configured to write data to the first buffer during a first execution instance of the first set of operations. The first set of operations is configured to write data to the second buffer during a second execution instance of the first thread. A second set of operations is configured to read the data from the first buffer during an instance of the second thread that executes contemporaneously with the second execution instance of the first set of operations. Determinations regarding access to the first buffer and second buffer by the first thread and second thread are self-contained within the first thread and second thread, respectively.

Abstract: A computer-implemented method for generating code based on a graphical model may include: translating the graphical model into a graphical model code, the graphical model code including a first graphical model code function; performing a lookup of the first graphical model code function in a hardware specific library, the hardware specific library comprising a plurality of relationships between graphical model code functions and hardware specific functions, where the first graphical model code function is one of the graphical model code functions; obtaining a matched hardware specific function based on the lookup, wherein the matched hardware specific function is one of the hardware specific functions from the hardware specific library; and modifying the graphical model code based on the matched hardware specific function.

Abstract: A computer-implemented method for generating code based on a graphical model may include: translating the graphical model into a graphical model code, the graphical model code including a first graphical model code function; performing a lookup of the first graphical model code function in a hardware specific library, the hardware specific library comprising a plurality of relationships between graphical model code functions and hardware specific functions, where the first graphical model code function is one of the graphical model code functions; obtaining a matched hardware specific function based on the lookup, wherein the matched hardware specific function is one of the hardware specific functions from the hardware specific library; and modifying the graphical model code based on the matched hardware specific function.

Abstract: A computer-implemented method for generating code based on a graphical model may include: translating the graphical model into a graphical model code, the graphical model code including a first graphical model code function; performing a lookup of the first graphical model code function in a hardware specific library, the hardware specific library comprising a plurality of relationships between graphical model code functions and hardware specific functions, where the first graphical model code function is one of the graphical model code functions; obtaining a matched hardware specific function based on the lookup, wherein the matched hardware specific function is one of the hardware specific functions from the hardware specific library; and modifying the graphical model code based on the matched hardware specific function.

Abstract: An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B.

Abstract: An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B.