Abstract: An on-substrate driver circuit for a display line of a liquid crystal display having an amplifier connected in conjunction with an amplifier input capacitor, a sample/hold capacitor and three switches. The circuit operates in a first compensation mode wherein the first and second of the switches connect both a null reference voltage and the amplifier output voltage to the amplifier input capacitor, effectively nulling out or compensating for offset between the turn-on threshold, and hence the output, of a plurality of amplifiers on the display. After compensation, the circuit is switched to an operational mode wherein the first and second switches are open and a third switch connects the analog display signal to the sample/hold capacitor. A second preferred embodiment employing a double buffer including two consecutive, serially connected amplifier stages as described is also disclosed.

Abstract: A method and apparatus for high-speed processing of video images of objects in a scene. Each pixel, in lines of bicolored pixels of a raster scanned video image containing at least one object, is identified as to the object of which the pixel corresponds. Adjacent bicolored pixels of the same color across a line are grouped into corresponding numbered pixel groups. Pixel groups of the same color are downwardly grouped into numbered blobs of pixel groups. When a next line pixel group occurs which is of the same color with more than one previous line pixel group, the next line pixel group is grouped as part of first occurring previous line blob. Additional pixel group matches occurring between pixel groups of a previous and next line are upwardly grouped to provide a common ancestor blob number to each blob of the pixel group in each additional pixel group match.

Abstract: A video converter operating in real time that responds to frames of N lines of video data in a non-interlaced format to form two fields of interlaced data without loss of any information. The converter operates with a minimum of two lines of memory storage capacity and a minimum of timing structure. The concept in accordance with the invention allows data of substantially any non-interlaced format to be converted for display on an interlaced display unit such as a standard TV system.