Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. In some examples, a device may include a memory die coupled with a substrate. Further, the device may include a die seal structure surrounding the memory die and coupled with the substrate. In some examples, the die seal may include multiple layers and the device may include an insulative material coupled with at least one layer of the multiples layers and a conductive material coupled with the insulative material. Additionally, the device may include a sensing circuit coupled with the conductive material. In some examples, the sensing circuit may be configured to generate a signal based on a charge accumulated in the conductive material.

Abstract: Provided in this disclosure is a hitch adapter having a base plate and a latch plate. The base plate includes a plurality of anchor points and first and second semicircular cutouts. The base plate also includes a plurality of connection points disposed radially about a center point. The latch plate includes a latch semicircular cutout and a plurality of connection points—equal to the quantity of base plate connection points and corresponding to the locations of the base plate connection points. The latch plate is disposed atop the base plate.

Abstract: Provided in this disclosure is a hitch adapter having a base plate and a latch plate. The base plate includes a plurality of anchor points and first and second semicircular cutouts. The base plate also includes a plurality of connection points disposed radially about a center point. The latch plate includes a latch semicircular cutout and a plurality of connection points—equal to the quantity of base plate connection points and corresponding to the locations of the base plate connection points. The latch plate is disposed atop the base plate.

Abstract: A semiconductor device including a substrate; a substrate; a memory array disposed on the substrate, the memory array including one or more memory planes, and a plurality of source region contact (SRC) nodes that are disposed on a backside surface of corresponding one of the one or more memory planes and above the substrate; a plurality of high-voltage (HV) diodes that are disposed in the substrate and that are connected to corresponding SRC nodes, the HV diodes including a first type dopant material; and a plurality of highly doped regions that are disposed in the substrate and that include a second type dopant material, each of the plurality of highly doped regions including a plurality of local maximum doping regions that are vertically aligned under a frontside surface of the substrate.

Abstract: An apparatus includes a first voltage domain including a first circuit configured to operate at a first supply voltage, a second voltage domain including second circuit configured to operate at a second supply voltage, and a drain-ballasted electrostatic discharge (ESD) protection circuit configured to electrically couple the first voltage domain and the second voltage domain, the drain-ballasted ESD protection circuit including a first NMOS transistor, a second NMOS transistor, a floating interconnect that electrically couples the first NMOS transistor to the second NMOS transistor, and a grounding resistor coupled to the first NMOS transistor and the second NMOS transistor.

Abstract: A microelectronic device comprises, a control circuitry structure comprising an active region including control logic circuitry at least partially within a semiconductive material; a bond pad on a backside of the control circuitry structure; a conductive contact vertically extending from the bond pad, through the semiconductive material, and to the control logic circuitry; and a dielectric-filled slit vertically extending into the semiconductive material and horizontally circumscribing the conductive contact, portions of the semiconductive material horizontally interposed between the conductive contact and the dielectric-filled slit. Additional microelectronic devices, memory devices, microelectronic device packages, and electronic systems are also described.

Abstract: A discharge circuit includes a transistor and a metal resistor connected to the transistor. The transistor includes a plurality of unit cells. The metal resistor includes a plurality of resistor portions corresponding to the plurality of unit cells. Each unit cell of the plurality of unit cells has a footprint and a corresponding resistor portion of the plurality of resistor portions is arranged within the footprint.

Abstract: A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: A data driven workflow solution that normalizes business communications by systematically recording related business communications from disparate communications channels in a common format such that the related business communications are automatically integrated into the associated business processes and which flow solution is flexible for capturing additional data elements or to adapt to changing tasks associated with the business processes is disclosed.

Abstract: Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.