Abstract: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.

Abstract: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.

Abstract: A memory cell array employs “source-biasing”, wherein a bias voltage is applied to the sources of one or more FETs within a memory cell to reduce their “off” state sub-threshold leakage currents. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs, and ground for FETs which are being read. A plurality of source-bias circuits provides the selectively switched bias voltages to the memory cells in the array.

Abstract: A memory cell array employs “source-biasing”, wherein a bias voltage is applied to the sources of one or more FETs within a memory cell to reduce their “off” state sub-threshold leakage currents. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs, and ground for FETs which are being read. A plurality of source-bias circuits provides the selectively switched bias voltages to the memory cells in the array.

Abstract: A static Random Access Memory (RAM) has a sense enable circuit. A user-determinable number of timing cells produces a timing bit line output in response to a wordline enable input. A sense timing control circuit is triggered by the timing bit line output. The sense timing control circuit produces a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier. A user can change the number of timing cells to optimize operation.

Abstract: A static Random Access Memory (RAM) has a sense enable circuit. A user-determinable number of timing cells produces a timing bit line output in response to a wordline enable input. A sense timing control circuit is triggered by the timing bit line output. The sense timing control circuit produces a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier. A user can change the number of timing cells to optimize operation.

Abstract: A BiCMOS input circuit which is capable of detecting signals below a particular range, such as ECL signals, is presented. The circuit is useful in conserving the number of pins in a BiCMOS integrated circuit in that a signal below normal ECL levels can trigger special functions, such as testing. The circuit has a plurality of CMOS inverter circuits connected in series with the input node of the first inverter connected to the input terminal of the circuit and the output node of the last inverter circuit connected to the output terminal of the circuit. Diode-connected bipolar transistor created a potential difference between V.sub.CC and the source electrode of PMOS transistor of each CMOS inverter circuit in a declining fashion from the first inverter to the last inverter. The last inverter circuit has no potential difference at all so that its output has a full CMOS swing.

Abstract: An imput buffer regenerative latch circuit useful in BiCMOS integrated circuits is presented. The ECL input signal terminal is connected to the base of a bipolar transistor. The emitter of the transistor is connected to one of two input/out nodes of a CMOS regenerative latch circuit by the source/drain path of a MOS transistor. The second input/output node is similar connected to the emitter of a second bipolar transistor by the source/drain path of a second MOS transistor. The base of the second bipolar transistor is held at a reference voltage midway in the ECL voltage range. Latching occurs very quickly when the CMOS latch is activated.