Abstract: Examples of an epitaxial-silicon wafer with a buried oxide layer are described herein. Examples of methods to manufacture an epitaxial-silicon wafer with a buried oxide layer are also described herein. In some examples, material may be removed from an epitaxial-silicon wafer at a surface opposite an epitaxial surface layer until the epitaxial-silicon wafer is a specified thickness. The thinned epitaxial-silicon wafer may be bonded to an oxidized-silicon wafer at an oxidized surface forming a buried oxide layer.

Abstract: A temporary optical wave diffusion-promoting film is adhered to a lidded microelectromechanical systems (MEMS) wafer. Testing is performed on the lidded MEMS wafer using an interferometer directed towards the temporary optical wave diffusion-promoting film applied to the lidded MEMS wafer. The temporary optical wave diffusion-promoting film is peeled from the lidded MEMS wafer to remove the temporary optical wave diffusion-promoting film from the lidded MEMS wafer after performing the testing.

Abstract: A temporary optical wave diffusion-promoting film is adhered to a lidded microelectromechanical systems (MEMS) wafer. Testing is performed on the lidded MEMS wafer using an interferometer directed towards the temporary optical wave diffusion-promoting film applied to the lidded MEMS wafer. The temporary optical wave diffusion-promoting film is peeled from the lidded MEMS wafer to remove the temporary optical wave diffusion-promoting film from the lidded MEMS wafer after performing the testing.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A reference element comprising a tunnel-junction device may be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

Abstract: A method of manufacturing a nanowire filament includes forming and fusing actions. In a forming action, close proximity conductors are formed. In another forming action, a junction oxide is formed between the close proximity conductors. In a fusing action, a nanowire filament is fused between the close proximity conductors, through the junction oxide. A circuit is also provided, having first and second close proximity conductors, and a nanowire filament fused between the close proximity conductors.

Abstract: This invention relates to a method for forming a nano-imprinted photonic crystal waveguide, comprising the steps of: preparing an optical film on a substrate; preparing a template having a plurality of protrusions of less than 500 nm in length such that the protrusions are spaced a predetermined distance from each other; heating the film; causing the template to press against the heated film such that a portion of the film is deformed by the protrusions; separating the template from the film; and etching the film to remove a residual layer of the film to form a nano-imprinted photonic crystal waveguide.

Abstract: A self-assembled photonic crystal is formed using a template made by nanoimprint lithography. A layer of imprintable material is deposited on a substrate, a pattern is imprinted in the imprintable material to form a template (the pattern of the template being adapted to substantially constrain colloidal particles to a predetermined lattice), and colloidal particles are introduced onto the template, substantially filling the predetermined lattice.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A method of manufacturing a nanowire filament includes forming and fusing actions. In a forming action, close proximity conductors are formed. In another forming action, a junction oxide is formed between the close proximity conductors. In a fusing action, a nanowire filament is fused between the close proximity conductors, through the junction oxide. A circuit is also provided, having first and second close proximity conductors, and a nanowire filament fused between the close proximity conductors.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: Tunnel-junction structures are fabricated by any of a set of related methods that form two or more tunnel junctions simultaneously. The fabrication methods disclosed are compatible with conventional CMOS fabrication practices, including both single damascene and dual damascene processes. The simultaneously formed tunnel junctions may have different areas. In some embodiments, tub-well structures are formed with sloped sidewalls. In some embodiments, an oxide-metal-oxide film stack on the sidewall of a tub-well is etched to form the tunnel junctions. Memory circuits, other integrated circuit structures, substrates carrying microelectronics, and other electronic devices made by the methods are disclosed.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A method of manufacturing a nanowire filament includes forming and fusing actions. In a forming action, close proximity conductors are formed. In another forming action, a junction oxide is formed between the close proximity conductors. In a fusing action, a nanowire filament is fused between the close proximity conductors, through the junction oxide. A circuit is also provided, having first and second close proximity conductors, and a nanowire filament fused between the close proximity conductors.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: Tunnel-junction structures are fabricated by any of a set of related methods that form two or more tunnel junctions simultaneously. The fabrication methods disclosed are compatible with conventional CMOS fabrication practices, including both single damascene and dual damascene processes. The simultaneously formed tunnel junctions may have different areas. In some embodiments, tub-well structures are formed with sloped sidewalls. In some embodiments, an oxide-metal-oxide film stack on the sidewall of a tub-well is etched to form the tunnel junctions. Memory circuits, other integrated circuit structures, substrates carrying microelectronics, and other electronic devices made by the methods are disclosed.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.