Abstract: A computer system is disclosed having a bus capability determination mechanism. In a preferred embodiment, the computer system includes a backplane having sockets into which system and peripheral boards may be inserted. The sockets are coupled together by a backplane bus that includes a bus capability line. Each board preferably includes a voting circuit that, when enabled, limits the voltage on the capability signal line to no more than a predetermined voltage that is indicative of the capability of the board. The voltage on the capability signal line will thus be determined by the board having the lowest voltage limit. The clock source for the bus can then be set to the clock rate indicated by the voltage on the capability signal line. Zener devices are preferably used to carry out the voting operation, and may be disabled after the voting operation is complete.

Abstract: A computer system is disclosed having a bus capability determination mechanism. In a preferred embodiment, the computer system includes a backplane having sockets into which system and peripheral boards may be inserted. The sockets are coupled together by a backplane bus that includes a bus capability line. Each board preferably includes a voting circuit that, when enabled, limits the voltage on the capability signal line to no more than a predetermined voltage that is indicative of the capability of the board. The voltage on the capability signal line will thus be determined by the board having the lowest voltage limit. The clock source for the bus can then be set to the clock rate indicated by the voltage on the capability signal line. Zener devices are preferably used to carry out the voting operation, and may be disabled after the voting operation is complete.

Abstract: A data communication system embodying an apparatus and a method provides simultaneous paths between a plurality of transmit ports and a plurality of receive ports for transmitting therebetween data identifying their destination receive ports. Such data are signals which are constructed in accordance with a standard serial protocol for frame element communication, such as HDLC (High-level Data Link Control). The system is assembled in a chassis containing a backplane and multiple cards having transmit and receive ports through which the cards couple the backplane.

Abstract: In an industrial process control system, in which the process is controlled via multiplicity of I/O data points communicating with a computer system controller, errors in the addressing signals selecting the I/O data points are prevented from causing the incorrect setting or reading out incorrect data from wrongly selected data points. A multibit parity signal is generated from the address signals as presented at the output of the computer controller and this parity signal is compared with a second multibit parity signal generated from the address signals as applied to the I/O racks on which the I/O data points are organized. If the parity signals don't compare, the change of the setting of or the read out of valid data from the I/O data point selected by the address signal is prevented.