Abstract: A system enables optical communication with direct conversion of the electrical signal into an optical signal with an array of optical sources. The use of the array of optical sources can eliminate the need for a large serializer/deserializer (SERDES). With an array of optical sources, the optical communication can occur at lower power and lower frequency per optical source, with multiple parallel optical sources combining to provide a signal.

Abstract: Composite IC die structures comprising a first IC die that has a first region directly bonded to a second IC die across a hybrid-bond interface and a topographic feature extending from a second region of the first IC die. In some examples, a hybrid bond interface is fabricated prior to forming a topographic IC die feature. In other examples, a hybrid bond interface is fabricated after forming a topographic IC die feature. A PIC die comprising a planar optical waveguide further includes an optical coupler protruding from a region of the die. In another region of the PIC die metallization features are embedded with a dielectric material suitable for forming a hybrid bond with a surface of an EIC die. Scaling of the directly bonded interconnections between the PIC and EIC die may facilitate further disintegration of the optical and electrical domains within a heterogenous chip/chiplet assembly.

Abstract: Embodiments disclosed herein include an apparatus that comprises a first layer with a first dielectric material, a second layer with a second dielectric material embedded within the first layer, where the second dielectric material has a higher index of refraction than the first dielectric material, and a first contact that is electrically conductive embedded in the first layer. In an embodiment, a third layer comprises a third dielectric material, a fourth layer comprising a fourth dielectric material and is embedded within the third layer, where the fourth dielectric material has a higher index of refraction than the third dielectric material, and a second contact that is electrically conductive embedded in the third layer. In an embodiment, the first layer directly contacts the third layer, the second layer directly contacts the fourth layer, and the first contact directly contacts the second contact.

Abstract: Embodiments disclosed herein include an apparatus that includes a substrate with a first optical waveguide within the substrate, an optical ring resonator within the substrate, and a second optical waveguide within the substrate. In an embodiment, the first optical waveguide and the second optical waveguide are offset from each other in a vertical direction and a horizontal direction. In an embodiment, the optical ring resonator is between the first optical waveguide and the second optical waveguide in the horizontal direction.

Abstract: Devices and systems with shifted out-of-plane light propagation, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes a first optical waveguide, a second optical waveguide, and one or more passive optical components. The first and second optical waveguides are optically coupled via the passive optical components. Moreover, the passive optical components are to shift light propagation out of plane between the first and second optical waveguides.

Abstract: Technologies for a compact and low-crosstalk multilayer waveguide stack are disclosed. In an illustrative embodiment, a photonic integrated circuit (PIC) die includes a 3D array of waveguides arranged in a multilayer stack. Individual waveguides have a propagation constant different from the propagation constant of neighboring waveguides, which can reduce crosstalk between neighboring waveguides. In an illustrative embodiment, the propagation constant can be controlled by changing the width of individual waveguides. In other embodiments, the propagation constant can be controlled by changing any suitable parameter, such as the height of the waveguides, the core of the waveguides, the cladding of the waveguides, etc.

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

Abstract: An apparatus comprising a chip comprising a plurality of micro-emitters, the micro-emitters to couple to a plurality of data lines and to an optical fiber, wherein the micro-emitters are to generate optical signals for parallel transmission through the optical fiber, the optical signals corresponding to data communicated on the data lines.

Abstract: Technologies for optical equalizers with metasurfaces are disclosed. In an illustrative embodiment, an optical equalizer can be formed from two metasurfaces. The metasurfaces reflect light in different directions depending on the spatial mode of the light. The metasurfaces can be used to change the optical path length of different modes of light from an optical input to an optical output, such as from an optical fiber to a photodiode. The optical equalizer can delay some modes of light relative to other modes, partially or fully compensating for mode dispersion in a multi-mode optical fiber.

Abstract: Technologies for bridge dies for optical interconnects are disclosed. In an illustrative embodiment, build-up layers are adjacent a substrate, and a bridge die and a photonic integrated circuit (PIC) die are each mounted on the substrate. An xPU die is mounted on the build-up layers and the bridge die, and another electronic integrated circuit (EIC) die is mounted on the bridge die and the PIC die. The bridge die can both transfer electronic signals between the XPU and the EIC die as well as provide power signals from the substrate through one or more through-silicon vias defined in the bridge die. The power signals can be provided to the PIC die, which allows for a shorter path for a power signal compared to passing the power signal through the build-up layers. The shorter path for the power signal can improve power delivery integrity and reduce parasitic power delivery drops.

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or electronic integrated circuits. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

Abstract: A system enables optical communication with direct conversion of the electrical signal into an optical signal with an array of optical sources. The use of the array of optical sources can eliminate the need for a large serializer/deserializer (SERDES). With an array of optical sources, the optical communication can occur at lower power and lower frequency per optical source, with multiple parallel optical sources combining to provide a signal.

Abstract: Embodiments disclosed herein include waveguides. In an embodiment, a waveguide comprises a conductive shell and a first ridge within the conductive shell. In an embodiment, the first ridge extends away from the conductive shell. In an embodiment, the waveguide further comprises a first core over the first ridge, where the first core comprises a first dielectric material with a first permittivity. In an embodiment, the waveguide may further comprise a second core embedded in the first core, where the second core comprises a second dielectric material with a second permittivity that is greater than the first permittivity.

Abstract: An apparatus comprising a chip comprising a plurality of micro-emitters, the micro-emitters to couple to a plurality of data lines and to an optical fiber, wherein the micro-emitters are to generate optical signals for parallel transmission through the optical fiber, the optical signals corresponding to data communicated on the data lines.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to thermally and/or electrically coupling a thermal die to the surface of a photonic integrated circuit (PIC) within an open cavity in a substrate, where the thermal die is proximate to a laser on the PIC. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments disclosed herein include waveguides. In an embodiment, a waveguide comprises a conductive shell and a first ridge within the conductive shell. In an embodiment, the first ridge extends away from the conductive shell. In an embodiment, the waveguide further comprises a first core over the first ridge, where the first core comprises a first dielectric material with a first permittivity. In an embodiment, the waveguide may further comprise a second core embedded in the first core, where the second core comprises a second dielectric material with a second permittivity that is greater than the first permittivity.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.