Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.

Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.

Abstract: Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure.

Abstract: Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure.

Abstract: Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure.

Abstract: Structures and methods are provided for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion. A dielectric material is disposed on at least one of the first and second electrical structures. This dielectric material is a low modulus material which has a high ultimate elongation property (LMHE dielectric). Preferably, the LMHE dielectric has a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least 20 percent. The LMHE dielectric can be photo patternable to facilitate formation of via openings therein and a metal layer is formed above the LMHE dielectric which has conductors capable of expanding or contracting with the dielectric.

Abstract: Chips first packaging structures and methods of fabrication are presented which employ electroless metallizations. An electroless barrier metal is disposed over and in electrical contact with at least one aluminum contact pad of the chips first integrated circuit. The electroless barrier metal is a first electroless metal and is a different material than the at least one aluminum contact pad. An electroless interconnect metal is disposed above and electrically contacts the electroless barrier metal. The electroless interconnect metal is a second electroless metal, which is different from the first electroless metal. As an example, the electroless barrier metal comprises electroless nickel and the electroless interconnect metal comprises electroless copper.

Abstract: A piezoelectric relay requiring less piezoelectric material than conventional piezoelectric relays is disclosed. The relay differs from conventional relays in that the contacts are touching with essentially no force applied between the contacts when no power is applied to the relay.

Abstract: An area saving dielectrically isolated semiconductor structure is disclosed which allows for the merger of a plurality of active devices, which share a common terminal, in a single dielectrically isolated (DI) island, or tub. In particular, an isolation groove is formed in the bottom of the DI tub and extends upwards toward the top surface of the semiconductor structure. The common diffusion region associated with the common terminal is located in the DI tub directly over the isolation groove. The isolation groove and common diffusion region thus separate the single DI tub into isolated sections, where a separate active device can be formed in each section. Isolation is achieved through the interaction of the groove with the common diffusion region to "pinch off" the conductive channel between devices in the DI tub. In a preferred embodiment, an inverted V-shaped isolation groove is utilized so as not to complicate the fabrication process.

Abstract: A method of forming a multilayer metallization pattern using siloxane polyimide dielectric layers comprises forming the first siloxane polyimide layer, laser etching holes in the first layer, plasma etching the first layer to be sure the holes are clean, then cleaning the surface of the first layer in an etchant for silicon oxide, after which the metallization layer is formed and patterned and a second siloxane polyimide layer is formed thereover with good adhesion.

Abstract: An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.

Abstract: A method and apparatus for detecting and locating defective crosspoint switches in a path consisting of a plurality of conducting segments connected by switch points is disclosed. The method and apparatus utilize the change in capacitance of the path which occurs when the switches are operated in a predetermined order.

Abstract: A circuit for driving an output between two voltage states in response to a control signal is disclosed. The circuit requires a very small amount of power in its quiescent state. The circuit comprises a first switch including first and second control terminals that provides a conductive path from a first source of potential to an output terminal when the potential difference between the control terminals is less than a first predetermined threshold value and for electrically isolating the first source of potential from the output terminal when the potential difference between the control terminals is greater than the first predetermined threshold value, and a second switch that provides a conductive path between a second source of potential and the output terminal when the first switch electrically isolates the first source of potential from the output terminal.

Abstract: A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operations, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.

Abstract: A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operation, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.

Abstract: High voltage semiconductor devices include a drift layer region underlying a field gate electrode, the drift layer region having a selected charge density of lesser magnitude than the charge density of the remainder of the drift layer. This tailoring of the charge density of the drift layer region lowers the pinch-off voltage of a MOSFET inherent in the drift layer region. This lower pinch-off voltage decreases the potential of a device buried-layer when the device is in a reverse blocking mode of operation.

Abstract: Control circuitry used with the combination of a control switch (typically a gated diode switch GDS) which is coupled to a control (gate) terminal of a like load switch which consists essentially of first and second p-n-p transistors. The collector of the first p-n-p transistor is coupled to an anode of the control switch. The emitter of the first p-n-p transistor is coupled to the base of the second p-n-p transistor and to a control circuitry input terminal. The collector of the second p-n-p transistor is coupled to a gate terminal of the control switch. The control circuitry limits undesirable current flow into the load switch and has fewer components than commonly used control circuitry which performs a like function.

Abstract: The present invention relates to an improved Schottky barrier device wherein the leakage current present in the reverse bias mode attributed to the presence of an electric field at the Schottky barrier (18) is significantly reduced by the inclusion of one or more field shields (22), P.sup.+ -type diffusions located under the metal anode (16) of the Schottky barrier device at the Schottky barrier (18). The P.sup.+ -type field shields, which are disposed in a pattern on the surface of the Schottky barrier, reduce the surface electric field present, thereby significantly reducing the leakage current related thereto.