Abstract: A memory cache device for a CD-ROM for use with a host computer capable of initially filling a clone area of the hard disk with data from the compact disc using a sequential striped fill process for copying a plurality of blocks of data from the compact disc to the hard disk, the process comprising the steps of: accessing a first block of data of a sequence of data blocks from the compact disc and copying the first block onto the hard disk, accessing a second block of data in the sequence of data blocks from the compact disc and not copying the second block to the hard disk, and accessing a third block of data in the sequence of data blocks from the compact disc and copying the third block onto the hard disk, the fill process continuing until the entire capacity of the hard disk devoted to cloning the compact disk is full, while leaving sufficient area for storage of blocks not initially copied in the fill process.

Abstract: A controller system for a CD-ROM drive or other slow access device such as a magneto-optical device using a conventional hard disk drive as a cache memory. In some embodiments, the hard disk cache is partitioned to use a portion thereof to clone the most often used data blocks on the CD-ROM disk such as the directory/file allocation table, while the balance of the hard disk is used to cache some or all of the balance of the CD-ROM disk using conventional cache memory least recently used rules. Three bus controllers for the host computer, CD-ROM drive and the hard disk cache are controlled by a microprocessor which runs a control program that implements the cloning and cache rules. The three bus controllers are connected by a DMA bus for faster transfer of data. The microprocessor controls the directions of the DMA transfers by data written to a control register.

Abstract: A converter for coupling a single-ended and a differential SCSI bus that facilitates the use of the ARB, SELECTION, and RESELECTION phases of the SCSI protocol.

Abstract: In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs).