Abstract: The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance data. Also, the invention provides an instruction cache that modifies hints and writes them back. As runtime hint updates are stored in instructions, the impact of the updates is not limited by the limited memory capacity local to a processor. Also, there is no conflict between hardware and software hints, as they can share a common encoding in the program instructions.

Abstract: A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for fetching native instructions from a memory subsystem (such as an EM fetch engine) is interfaced with an engine that processes emulated instructions (such as an x86 engine). This is achieved using a handshake protocol, whereby the x86 engine sends an explicit fetch request signal to the EM fetch engine along with a fetch address. The EM fetch engine then accesses the memory subsystem and retrieves a line of instructions for subsequent decode and execution. The EM fetch engine sends this line of instructions to the x86 engine along with an explicit fetch complete signal. The EM fetch engine also includes a fetch address queue capable of holding the fetch addresses before they are processed by the EM fetch engine. The fetch requests are processed such that more than one fetch request may be pending at the same time.

Abstract: Wires that carry bits of an instruction syllable of an instruction bundle are routed to first and second branch execution units. The wires are routed over the first branch execution unit. When the first branch execution unit is configured to calculate a branch target of a long IP-relative branch instruction occupying multiple syllables of an instruction bundle, the wires are coupled to the first branch execution unit. Otherwise, the wires are not coupled to the first branch execution unit.

Abstract: Compiled and linked program code having instructions grouped into bundles, wherein the instructions of each bundle are sequentially ordered, is patched by forming a patch bundle and one or more patch code bundles. This is done by writing a long IP-relative branch instruction into multiple syllables of the patch bundle, with the long IP-relative branch instruction providing a means of branching to patch code. Instructions which are similarly located in a bundle to be patched, and which precede the long IP-relative branch instruction, are copied into syllables of the patch bundle. Other instructions of the bundle to be patched are copied into ones of the one or more patch code bundles. The bundle to be patched is overwritten with the patch bundle, and the one or more patch code bundles are written into the patch code.

Abstract: In one embodiment of the invention, data values which are provided to a non-tagged, n-way cache are written into the cache in a non-count form. Whereas a counter tends to quickly saturate to one extreme or the other (e.g., all zeros or all ones), or briefly take on a value which approaches an extreme, a non-count data value (e.g., branch prediction history bits) tends to assume a wider variety of values.