Patents by Inventor James E. Nulty

James E. Nulty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7685705
    Abstract: A probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: March 30, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: James E. Nulty, James A. Hunter, Alexander J. Herrera
  • Patent number: 7332921
    Abstract: In one embodiment, a probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 19, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: James E. Nulty, James A. Hunter, Alexander J. Herrera
  • Patent number: 7112975
    Abstract: In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of holes may extend through the SOI layer and the plurality of probe dice, with each hole corresponding to a pad on a probe die. The anti-wafer structure may be advantageously used in an advanced probe card. Techniques for fabricating an anti-wafer and an advanced probe card are also disclosed.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: September 26, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Bo Jin, James E. Nulty
  • Patent number: 6890860
    Abstract: Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 ? of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl2/O2, HBr/O2, CF4/O2 or another etch having an etch rate of approximately 3000 ?/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: May 10, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Tinghao F. Wang, Usha Raghuram, James E. Nulty
  • Patent number: 6847218
    Abstract: In one embodiment, an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: January 25, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: James E. Nulty, Brenor L. Brophy, Thomas A. McCleary, Bo Jin, Qi Gu, Thurman J. Rodgers, John O. Torode
  • Patent number: 6784552
    Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: August 31, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: James E. Nulty, Christopher J. Petti
  • Publication number: 20020146897
    Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on said semiconductor body then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate. An etch stop layer is deposited adjacent said insulating layer followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer but retains the substantially rectangular lateral spacer profile of the first insulating layer.
    Type: Application
    Filed: March 31, 2000
    Publication date: October 10, 2002
    Inventors: James E. Nulty, Christopher J. Petti
  • Patent number: 6372634
    Abstract: A plasma etch chemistry and etch methodology is provided to improve critical dimension control for openings formed into and/or through a semiconductor thin film. According to an embodiment, the plasma etch chemistry includes an etchant mixture comprising a first etchant of the formula CxHyFz (where x≧2, y≧1 and z≧2) and a second etchant other than the first etchant to form the openings. The relationship of x, y and z may be such that y+z equals an even number ≦2x+2. According to an alternative embodiment, the plasma etch chemistry further includes strained cyclic (hydro)fluorocarbon. The plasma etch chemistry may be used to form openings in the layer in a single-etch step. In a further embodiment, the plasma etch chemistry described herein may etch less than the entire thickness of the layer, and a second plasma etch chemistry substantially free of the first etchant and strained cyclic (hydro)fluorocarbons etches the remainder of the layer to form the openings.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: April 16, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jianmin Qiao, Sanjay Thekdi, Manuj Rathor, James E. Nulty
  • Patent number: 6373679
    Abstract: An electrostatic or mechanical chuck assembly includes gas inlets only in an annulus-shaped peripheral portion and not in the central region of the chuck. The gas inlets are in fluid communication with one or more gas conduits and supply of the backside of a workpiece, such as a semiconductor wafer, with inert coolant gas or gases. The gas or gases supplied only to the peripheral region of the chuck effectively cool the central region of the chuck by at least two physical mechanisms, including the thermal conduction through the workpiece and diffusion of the gas or gases in the interstitial space(s) between the somewhat irregular facing surfaces of the chuck and of the backside of the workpiece.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: April 16, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jianmin Qiao, James E. Nulty, Paul Arleo, Siamak Salimian
  • Patent number: 6066555
    Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: May 23, 2000
    Assignee: Cypress Semiconductor Corporation
    Inventors: James E. Nulty, Christopher J. Petti
  • Patent number: 5562801
    Abstract: A method of etching an oxide layer is disclosed. First, a resist layer is formed on an oxide layer on a substrate. Next, a photosensitive layer is formed on the oxide layer and patterned to expose regions of the oxide layer to be removed. The exposed regions may overlie a nitride layer, and may overlie a structure such as a polysilicon gate. The etch is performed such that polymer deposits on the photosensitive layer, thus eliminating interactions between the photosensitive layer and the plasma. In this way, a simple etch process allows for good control of the etch, resulting in reduced aspect ratio dependent etch effects, high oxide:nitride selectivity, and good wall angle profile control.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: October 8, 1996
    Assignee: Cypress Semiconductor Corporation
    Inventor: James E. Nulty
  • Patent number: 5468342
    Abstract: A method of etching openings in oxide layers is disclosed. A hard mask layer is formed on the oxide layer. The hard mask layer is then patterned by a photoresist layer and an etch is performed to form openings in the hard mask. Next, the patterning layer may be removed and an etch is performed to remove the oxide in the regions defined by the hard mask layer openings. The etch with hard mask has minimized aspect ratio dependency, so that openings of different sizes may be formed simultaneously. An etch that may be carried out with Freon 134a (C.sub.2 H.sub.2 F.sub.4) to provide superior oxide:nitride selectivity is also disclosed. Additionally, the etch may be carried out at high temperature for improved wall profile without loss of selectivity. For deep openings, a two step etch process is disclosed, with a polymer clean step between the etches to remove polymer build up from first etch, and allow the etch to proceed to an increased depth.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: November 21, 1995
    Assignee: Cypress Semiconductor Corp.
    Inventors: James E. Nulty, Pamela S. Trammel
  • Patent number: 5441596
    Abstract: A method for forming a stable plasma, particularly in the high power and low pressure ranges. The method may be used in a plasma system such as that used for a plasma etch. First, the radio frequency power is turned on under low power and high pressure. The plasma is allowed to stabilize without tuning. Next, the pressure is dropped to the desired operating level and the tuning system is engaged. After tuning at the low power and low pressure, the radio frequency power is ramped to the desired level. Finally, the system is again tuned at the higher power.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: August 15, 1995
    Assignee: Cypress Semiconductor Corporation
    Inventor: James E. Nulty
  • Patent number: 5045149
    Abstract: A method and an apparatus for detecting the endpoint in a plasma etching process is disclosed. The invention uses a positive filter and a negative filter simultaneously to generate a first and a second signal respectively. The first and second signals are combined to form a combined signal. A change in the combined signal is indicative of the endpoint.
    Type: Grant
    Filed: June 22, 1990
    Date of Patent: September 3, 1991
    Assignee: VLSI Technology, Inc.
    Inventor: James E. Nulty
  • Patent number: 5013400
    Abstract: A two-step process for forming champagne profiles on semiconductor wafers that provide, when metallized, good reliability, microcracking-free contacts and vias is disclosed. Dry etch apparatus having electrodes in a triode configuration, two plasma forming regions, and a pressure control system operative to provide a wide setpoint pressure range is also disclosed.
    Type: Grant
    Filed: January 30, 1990
    Date of Patent: May 7, 1991
    Assignee: General Signal Corporation
    Inventors: Howard S. Kurasaki, Barbara F. Westlund, James E. Nulty, E. John Vowles
  • Patent number: 4954212
    Abstract: A plasma etching endpoint detection system and method for plasma etching systems generates an endpoint signal when the etching system completes the etching of a designated layer on a semiconductor wafer and begins etching the layer below the designated layer. An impedance transformation circuit is tuned so that the selected tuning point has a predefined relationship to the point at which minimum power reflection occurs. As a result, when the etching system completes the etching of a designated layer, the amount of power reflected by the plasma etcher will change in a predefined fashion so as to facilitate the generation of an endpoint signal. In one embodiment, a tuning capacitor in the etcher's impedance transformation circuit is set at a level at which it is known that the amount of reflected power will increase when the designated layer has been completely etched. As a result, the intensity of light generated in the plasma will decrease at the endpoint of etching the designated layer.
    Type: Grant
    Filed: September 26, 1989
    Date of Patent: September 4, 1990
    Assignee: VLSI Technology, Inc.
    Inventors: Calvin T. Gabriel, James E. Nulty