Abstract: Systems and methods for selecting advertisements for presentation in a map space are disclosed. Map requests are received, map spaces identified, advertisement bids are received for advertisement space within the map spaces, and advertisements are selected for presentation in the map space based on the advertisement bids. The advertisement bids can be selected through an auction.

Abstract: Systems and methods for selecting advertisements for presentation in a map space are disclosed. Map requests are received, map spaces identified, advertisement bids are received for advertisement space within the map spaces, and advertisements are selected for presentation in the map space based on the advertisement bids. The advertisement bids can be selected through an auction.

Abstract: Systems and methods for selecting advertisements for presentation in a map space are disclosed. Map requests are received, map spaces identified, advertisement bids are received for advertisement space within the map spaces, and advertisements are selected for presentation in the map space based on the advertisement bids. The advertisement bids can be selected through an auction.

Abstract: Systems and methods for selecting advertisements for presentation in a map space are disclosed. Map requests are received, map spaces identified, advertisement bids are received for advertisement space within the map spaces, and advertisements are selected for presentation in the map space based on the advertisement bids. The advertisement bids can be selected through an auction.

Abstract: Systems and methods for selecting advertisements for presentation in a map space are disclosed. Map requests are received, map spaces identified, advertisement bids are received for advertisement space within the map spaces, and advertisements are selected for presentation in the map space based on the advertisement bids. The advertisement bids can be selected through an auction.

Abstract: Systems and methods for selecting advertisements for presentation in a map space are disclosed. Map requests are received, map spaces identified, advertisement bids are received for advertisement space within the map spaces, and advertisements are selected for presentation in the map space based on the advertisement bids. The advertisement bids can be selected through an auction.

Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract: A voltage level shifter comprises a plurality of PMOS transistors coupled in series with NMOS transistors to form a plurality of pull-down inverters. When the second voltage level is enabled to connect, the pull-down inverters pull down faster than the pull-down NMOS transistors alone, and thus, the pull-up PMOS transistors pull up immediately to connect the first voltage level to the second voltage level. Thus, the PMOS transistors added to form pull-down inverters improve the switching time and eliminate the kinks in the output voltage.

Abstract: A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

Abstract: Attaining low standby power consumption in SRAM cells by reducing the current leakage through the transistors when they are switched off. The reduction is accomplished by raising the grounding voltage of the transistors, thereby reducing the source-drain voltage differential across the transistors, and enhancing the current limiting body effect, which in turn results in leakage current reduction. The grounding voltage is raised by a diode or other current-independent voltage modification means, such as an added voltage supply.

Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path means, and an output logic gate. The signal-path means coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract: A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

Abstract: A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a ‘low’ to storing a ‘high’. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.

Abstract: A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a ‘low’ to storing a ‘high’. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.

Abstract: A driver circuit for use in an array of picture elements in a liquid crystal display is capable of displaying one set of image data while receiving a second set of image data. A first select switch transistor responsive to a first select signal controls the coupling of a first image to a first storage capacitor. A second select switch transistor responsive to a second select signal controls the coupling of a second image to a second storage capacitor. The first storage capacitor may be selectively coupled to an output node by means of a first enable switch transistor responsive to a first enable signal. The second storage capacitor may be selectively coupled to the same output node by means of a second enable switch transistor responsive to a second enable signal. By proper manipulation of the switch transistors, one storage capacitor may be coupled to the output node while the other storage capacitor is isolated from the output node and receiving new image data.

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

Abstract: A voltage regulator circuit that receives an input signal and provides an output signal that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. If the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit is disabled and one of a plurality of voltage maintaining subcircuit takes control so that the output voltage remains at the desired voltage for the internal circuit.

Abstract: A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.

Abstract: A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.

Abstract: A fuse circuit includes a fusible element and a feedback path which causes the circuit to behave as if the fusible element is fully blown even though the fusible element in fact is partially intact. While a partially intact fuse normally would result in a continuous drain of power, the feedback path cuts off the current flow through the partially intact fusible element.