Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

Abstract: An MOS memory cell of the static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series coupling transistors connecting storage nodes to complementary precharged data lines. The coupling transistors are turned on in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. Both transistors are turned on at the same time for read or write operations.

Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process (with implants for self-alignment), modified to include P-channel transistors and to allow three levels of interconnects. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. The source and drain regions, N+ or P+, are defined prior to the polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

Abstract: An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified to allow three levels of interconnects. A P-type substrate is used as the starting material, with N+ source and drain regions defined prior to a polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Abstract: An MOS memory cell of the static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series coupling transistors connecting storage nodes to complementary precharged data lines. The coupling transistors are turned on in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. Both transistors are turned on at the same time for read or write operations.