Abstract: In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a STMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into a sum and a carry vector. The two least significant bits of the sum vector and the LSB of the carry vector are dropped before being input to the 36-bit SIMD adder. The two resultant 8-bit vectors are added by the 36-bit adder to directly generate the average pixel value result.

Abstract: In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a SIMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into a sum and a carry vector. The tow least significant bits of the sum vector and the LSB of the carry vector are dropped before being input to the 36-bit SIMD adder. The two resultant 8-bit vectors are added by the 36-bit adder to directly generate the average pixel value result.

Abstract: A row-wise technique may be utilized for determining a fractional matching block in a motion estimation vector algorithm. By interpolating and calculating a sum of absolute differences on a row-wise basis, a more efficient algorithm may be implemented. On a row-by-row basis, the corresponding interpolated values are updated and those values, once updated, may be compared to determine the best match among the potential fractional matching blocks. As a result, a fractional matching block may be identified to determine the motion vector to a greater degree of accuracy.