Abstract: Certain embodiments are directed to methods, devices, and/or systems for viewing and imaging all or most of the surface area of a three-dimensional (3-D) object with one or more two-dimensional (2-D) images.

Abstract: Certain embodiments are directed to a biofluid flow assist device comprising (a) a collar configured to wrap at least partially around a subject's neck or limb; (b) at least one biofluid flow assist mechanism configured to be position over a target when the collar is positioned on the subject's neck or limb; and (c) a controller operatively connected to the biofluid flow assist mechanism. In certain aspects the biofluid is blood, lymph, and/or cerebrospinal fluid (CSF).

Abstract: Methods, devices, and/or systems for the programming or training of a prosthetic and/or orthotic device.

Abstract: Embodiments are directed to devices configured to assist the flow of fluids in the body. The device comprises a covering for placing on the skin of a patient having protrusions which can contact the skin. The protrusions have a base proximal to a surface of the covering and an outer edge distal to the surface of the covering. Protrusions can be configured in an array, in a line perpendicular to desired fluid flow or in a spiral configuration, such that fluid flow is enhanced in the appropriate direction. The device can be configured as a prosthesis, an orthotic, a liner for a prosthesis or orthotic, or a wrap or covering that is positioned around a body part. The body part can be part of a lower limb, part of an upper limb, or other body part.

Abstract: A unitary layered ceramic structure is disclosed which comprises co-sintered layers. The co-sintered structure comprises a sintered central layer of yttria stabilized zirconia ("YSZ") which is about 8 mole percent yttria and having a density of at least about 95% of theoretical, and sintered outer layers of strontium lanthanum manganite ("LSM") having the approximate molecular composition La.sub.0.8 Sr.sub.0.2 MnO.sub.3, having a density from about 50 to about 60% of theoretical, and having interconnected porosity from about 40 to 50% with an interconnected pore diameter from about one micron to about five microns. The sintered central layer is sandwiched by and bonded and sintered to the outer layers and is essentially free of significant amounts of manganese.A process for making the unitary composition-of-matter is also disclosed which involves tape casting a LSM tape and then on top thereof casting a YSZ tape. The process comprises presintering LSM powder at 1250.degree. F.

Abstract: An unitary layered ceramic structure is disclosed which comprises co-sintered layers. The co-sintered structure comprises a sintered central layer of yttria stabilized zirconia ("YSZ") which is about 8 mole percent yttria and having a density of at least about 95% of theoretical, and sintered outer layers of strontium lanthanum manganite ("LSM") having the approximate molecular composition La.sub.0.8 Sr.sub.0.2 MnO.sub.3, having a density from about 50 to about 60% of theoretical, and having interconnected porosity from about 40 to 50% with an interconnected pore diameter from about one micron to about five microns. The sintered central layer is sandwiched by and bonded and sintered to the outer layers and is essentially free of significant amounts of manganese.A process for making the unitary composition-of-matter is also disclosed which involves tape casting a LSM tape and then on top thereof casting a YSZ tape. The process comprises presintering LSM powder at 1250.degree. F.

Abstract: A high efficiency dropout regulator (60) drives an output transistor (22) with a PNP transistor (52) if the overhead voltage from input (14) to output (26) is below a predetermined voltage. If the overhead voltage exceeds the predetermined voltage, then a second PNP transistor (64) and an NPN transistor (72) are used to drive the output transistor (22), resulting in a large reduction of power loss. The current drawn from the output transistor (22) by the NPN transistor (72) is returned to the output.

Abstract: The embodiments of the invention provide mechanical and electrical appara for inexpensively and swiftly converting conventional firearms temporarily into marksmanship training devices. Illustratively, a number of different devices are shown for attaching marksmanship training and scoring apparatus to the weapon or weapon launcher and to enhance training realism without expending ammunition. Electrical circuits for improved marksmanship training and scoring also are shown and described.

Abstract: An illustrative embodiment of the invention provides marksmanship training in a realistic environment. A "light pen" is clamped to the muzzle of a weapon. The "light pen" and weapon are aimed at a microcomputer-generated target or videodisc-player-generated target on the screen of a television monitor. A trigger switch on the weapon is closed when the marksman perceives the correct orientation between the weapon and the target. The microcomputer calculates the proper trajectory of the simulated "round" based on the orientation of the "light pen" relative to the screen at the time the trigger switch is closed in order to generate and display the calculated shot impact point for the benefit of the trainee marksman.

Abstract: An assembly (28) of ceramic surfaces (21, 23), particularly refractory metal oxides and carbides, abutting a thin sheet (22) of metal susceptor material are placed in a chamber (10) of an enclosure (14) containing inert gas (36). An r.f. coil (24) is activated by power supply (26) to melt the susceptor (22) and adjacent zones (40, 42) of the ceramic. Reactive gas such as oxygen or a carbonizing gas (38) is then fed to the chamber (10) and reacts with the susceptor (22) to form compounds (47) which disperse and dissolve in the zones (40, 42). On cooling, a strong joint is formed. The susceptor may contain inner perforations (58) and outer perforations (56) to aid in distribution of heat.

Abstract: A vertical insulated gate field effect transistor having a first conductivity layer, a second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction.The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continuing the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.

Abstract: An electrical insulating coating of thermosetting polymeric material for a surge arrester valve element of silicon carbide particles bound together within a ceramic matrix, in which the coating is applied in powder form. Curing of the coating is effected either by a heating cycle following the application of the powder insulating coating, or by preheating of the valve element before application of the powder coating. Alternately, the insulating coating can be applied as a plasma spray, making post-curing unnecessary.

Abstract: A vertical insulated gate field effect transistor having a first first conductivity layer, a second second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction.The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continue the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.

Abstract: A buffer having a single input and a pair of outputs providing three unambiguous logic output states including a first output connected directly to the input and a second output connected to the junction of a common gate configured FET and an impedance. The input is also connected to the source and body of the FET and a voltage source is connected to the impedance. The first output varies with the input for a first polarity input signal and the second output varies with the input for the opposite polarity input signal.

Abstract: A memory having a P channel device for each storage element, complementary FET inverters as row drivers for reading and complementary FET devices connected in series as column drivers for reading. A P channel device and a resistor are connected to the source and drain of the N channel device of the row driver and a P channel device is provided as a column driver for the high writing or programming potential. The series P channel device of the column read driver is switched off during writing.

Abstract: The disclosure relates to methods of forming Insulated Gate Field Effect transistors and the product suitable for integrated circuits with channel lengths of 1 micron or less, the transistors being isolated from other transistors or other components in the circuit without the requirements of extra isolation steps. This is provided by means of a double diffusion which isolates the channel of the transistor from other elements in the circuit. Channel length is solely a function of the diffusion schedule through openings in the oxide through which the double diffusion takes place.