Abstract: A multi-requester arbitration circuit receives multiple asynchronous request signals and provides a first common timing signal from the request signals. A sample-and-hold circuit receives each of the request signals and produces corresponding output sample signals. The sample-and-hold circuit receives the first common timing signals. A time delay circuit produces a second timing signal from the first common timing signal. A storage circuit receives the output sample signals and produces corresponding output stored signals. The storage circuit receives the second timing signal. An arbitration circuit receives the output stored signals to select one of the request signals and provide at least an output control signal indicative thereof. The sample-and-hold circuit samples each of the request signals before the first common timing signals causes the sample-and-hold circuit to hold all request signals.