Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time.

Abstract: A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

Abstract: A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

Abstract: Embodiments of the invention provide a method, computer program product, etc. for analysis techniques to reduce simulations to characterize the effect of variations in transistor circuits. A method of simulating transistors in an integrated circuit begins by reducing a group of parallel transistors to a single equivalent transistor. The equivalent transistor is subsequently simulated, wherein only a portion of the parallel transistors are simulated. Next, the integrated circuit is divided into channel-connected components and simulated for the channel-connected components. A table is created for each type of channel-connected component; and parameterized across chip variation equations are calculated from results of the integrated circuit simulation. Moreover, table entries are created, which include a number of transistor types, a number of unique transistor primitive patterns, and/or a number of paths through each of the transistor primitive patterns.

Abstract: A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number of neighboring cells which must be explored. In every fourth iteration of the expansion process, corner cells may not be expanded. Reachable areas outside of conductors can also be explored.