Patents by Inventor James E. Vasck

James E. Vasck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of area compaction for integrated circuit layout design
    Patent number: 7904869
    Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: March 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kathleen C. Yu, Scott D. Hector, Robert L. Maziasz, Claudia A. Stanley, James E. Vasck
  • METHOD OF AREA COMPACTION FOR INTEGRATED CIRCUIT LAYOUT DESIGN
    Publication number: 20090158229
    Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Inventors: Kathleen C. Yu, Scott D. Hector, Robert L. Maziasz, Claudia A. Stanley, James E. Vasck