Abstract: An integrated circuit memory system includes capacitive storage memory cells capable of storing n bits of information on n capacitors associated with multiple emitters of a bilaterally conductive bipolar transistor. Each capacitor is coupled to a separate bit/sense line. Access of a storage cell is achieved by forward biasing the common base/collector junction of the bipolar transistor. Writing is achieved by driving the bit/sense lines to charge or discharge the storage capacitors during an access cycle. In reading, or sensing, the charged state of each storage capacitor is determined by sensing potential changes on the bit/sense lines during access. Fabrication of memory arrays is possible by any one of several different techniques, all of which are compatible with high speed bipolar logic circuits.