Abstract: A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.

Abstract: A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.

Abstract: A technique for powering gate drivers in a half-bridge configuration uses a single external power supply to power each gate driver. A single on-chip regulator regulates the positive turn-on voltage for each switch. The regulator overhead, is also used as the negative voltage for turn-off, thus transferring the low-frequency variation of the external power supply to the negative turn-off voltage. Accordingly, a single on-chip regulator generates both the positive turn-on voltage and the negative turn-off voltage. In at least one embodiment, reuse of the switch turn-off current further reduces on-chip power dissipation. The on-chip regulator's output filter capacitor discharges during turn-on of the external power switching device. During turn-off, the current that discharges the switch gate capacitance recharges the regulator filter capacitor.

Abstract: A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

Abstract: A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

Abstract: A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.

Abstract: A technique for powering gate drivers in a half-bridge configuration uses a single external power supply to power each gate driver. A single on-chip regulator regulates the positive turn-on voltage for each switch. The regulator overhead, is also used as the negative voltage for turn-off, thus transferring the low-frequency variation of the external power supply to the negative turn-off voltage. Accordingly, a single on-chip regulator generates both the positive turn-on voltage and the negative turn-off voltage. In at least one embodiment, reuse of the switch turn-off current further reduces on-chip power dissipation. The on-chip regulator's output filter capacitor discharges during turn-on of the external power switching device. During turn-off, the current that discharges the switch gate capacitance recharges the regulator filter capacitor.

Abstract: A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.