Abstract: A portable laser source includes a flash lamp assembly defining a hollow central channel, an elongate laser rod extending within the hollow channel for receiving a flash of light emitted by the surrounding flash lamp assembly, and a hermetically-sealed enclosure housing both the flash lamp assembly and the laser rod and including at least one optical transmission window for transmitting a laser beam emitted by the laser rod. Preferably, the flash lamp assembly is hermetically-sealed from the laser rod within the enclosure to maintain physical and electrical isolation of the laser rod from combustible and electrically conductive components of the flash lamp assembly. The combustible component of the flash lamp assembly can include Zr wool and an accelerant, or like materials for emitting a flash of light. The laser source can include a second window used to test the condition of the laser rod via application of an external test light to activate the laser rod within the sealed enclosure.

Abstract: A portable laser source includes a flash lamp assembly defining a hollow central channel, an elongate laser rod extending within the hollow channel for receiving a flash of light emitted by the surrounding flash lamp assembly, and a hermetically-sealed enclosure housing both the flash lamp assembly and the laser rod and including at least one optical transmission window for transmitting a laser beam emitted by the laser rod. Preferably, the flash lamp assembly is hermetically-sealed from the laser rod within the enclosure to maintain physical and electrical isolation of the laser rod from combustible and electrically conductive components of the flash lamp assembly. The combustible component of the flash lamp assembly can include Zr wool and an accelerant, or like materials for emitting a flash of light. The laser source can include a second window used to test the condition of the laser rod via application of an external test light to activate the laser rod within the sealed enclosure.

Abstract: A wheel sensor which is primarily located outside of a pneumatic tire includes a sensor for sensing one or more conditions within the pneumatic tire of a wheel and a connector configured to secure the sensor to the wheel rim; wherein the connector establishes a link between the medium inside the tire and the sensor; and includes a valve which seals when the sensor is removed from the rim and opens when the sensor is attached to the rim.

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the “fpr target”) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand.

Abstract: During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.

Abstract: A method for wrap detection in a microprocessor system, the system including a plurality of rename buffers. The method includes performing a two's complement subtraction of a completion pointer from a target pointer, wherein a carry out results from the subtraction. The method further includes comparing the carryout and a virtual bit associated with a location to produce a result. The result is compared to the most significant bit of the target pointer and if there is a match between the most significant bit of the second pointer and the result, an indication is made that the instruction may issue. A system for utilizing the above method of wrap detection includes a means for performing a two's complement subtraction of a completion pointer from a target pointer, wherein a carry out results from the two's complement subtraction.

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the “fpr target”) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports out-of-order floating point unit instruction execution. The FPSCR mechanism provides appropriate reporting of exceptions to a re-order buffer implemented within a data processing system to allow precise interrupts during out-of-order instruction execution. Additionally, the FPSCR mechanism allows for the retention of the appropriate status and control history information in an FPSCR rename buffer to allow the floating points status and control register to be maintained as though instructions were being executed in order. Additionally, the FPSCR mechanism generates the FPSCR's sticky exception status in concordance with reporting appropriate status to the previously mentioned re-order buffer and saving history into the FPSCR rename buffer.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all FPU instructions. In particular, instructions that directly alter FPSCR data values may be executed speculatively. Instructions of this type which may be de-serialized include the move-from FPSCR instruction, the move-to-condition register from FPSCR instruction, the move-to FPSCR field immediate instruction, the move-to FPSCR field instruction, the move-to FPSCR bit 0 instruction, the move-to FPSCR bit 1 instruction, as well as FPU register-to-register instructions having a recording bit set. Speculative execution is implemented by providing an accurate working FPSCR at the time the speculatively executing instruction sources FPSCR data. Moreover, the FPSCR mechanism re-establishes the working FPSCR when exceptions occur, or speculative execution is cancelled.

Abstract: A method and system for interchanging operands and loading such operands into a plurality of operand registers in an execution unit with the data processing system during execution of a complex instruction. A plurality of operands are stored within a register file, including a first operand and a second operand. An instruction is loaded into the first stage of the execution pipe within the execution unit, wherein the instruction has a plurality of fields. Such fields include a first and second field, containing a first and second operand pointer, respectively, for designating a value stored in the register file for loading into first and second operand registers, respectively. Next, the first and second operand pointers are interchanged between the first and second fields.

Abstract: A method and apparatus for looking up source matches in a central processing unit (CPU) is utilized to identify dependencies between instructions that have been renamed via buffer renaming techniques. In such instances, when a particular instruction's source is a previous instruction's destination, that match needs to be identified such that dependent relationships between instructions are maintained. The source lookup method and apparatus utilize an allocation pointer and deallocation pointer, which point to the rename buffer, to produce a comparison window. For a given source of a given instruction, the comparison window is used to compare whether the source in question has a match within the rename buffer. If only one match is found, that rename buffer location is flagged to indicate that this particular location has a dependent relationship with the current source in question. If more than one match has been identified, a selection is made to choose the buffer location closest to the allocation pointer.

Abstract: A selectable adder/hashing circuit generates a hashed virtual address from address operands within or derived from a program instruction. The hashed virtual address is used to address a translation lookaside buffer (TLB). The hashing function and addition function each comprise multiple steps. Some of the hashing function steps are performed in parallel with some of the steps of the addition function, and other of the hashing function steps are performed within other of the addition function steps. Therefore, the hashing function does not add delay over that required to produce an un-hashed virtual address from an addition function performed on the address operands. The hashing function can be enabled or disabled to meet the needs of the particular program environment. A method for generating the un-hashed address from the hashed address determines if the contents of the TLB location addressed by the hashed address match the unhashed virtual address.