Abstract: A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.

Abstract: A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.

Abstract: A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.

Abstract: Subject matter described pertains to managing problematic memory cells in a memory array.

Abstract: Subject matter described pertains to managing problematic memory cells in a memory array.

Abstract: Methods and apparatus are provided for identifying which symbol within a codeword corresponds to an information state read from a problematic memory cell. A method can include applying a programming signal to a memory cell, and determining whether the programming signal programs the memory cell approximately within an operational range of a physical property of the memory cell. The method can include identifying which symbol within a codeword corresponds to an information state read from the memory cell, if the memory cell was not programmed approximately within the operational range of the physical property. Identifying the symbol can be done with a flag in the codeword.

Abstract: Subject matter described pertains to managing problematic memory cells in a memory array.

Abstract: A power converter capable of providing a range of DC voltages to an external device and a method of providing a range of DC power are provided. The power converter comprises a supply circuit for receiving a request for DC power and for providing the requested DC power. The supply circuit comprises a detection circuit for sensing a connection to an external device, a source controller circuit for determining a DC output power required by the external device, and a converter circuit for generating the required DC output power. The external device comprises a device controller circuit for communicating the request for DC power. A first conductor provides a path for the device to communicate the required DC power to the power converter and for the power converter to supply the required DC power. A second conductor provides a common reference for conducting return current to the power converter.

Abstract: Two embodiments for distributing DC power in a building are provided. In the first embodiment, a centralized DC power converter is connected to the building's standard AC power wiring. The centralized DC power converter generates DC power for at least one DC-powered electronic device. The DC power is routed to DC outlets throughout the building over DC conductor sets. A second embodiment embeds a DC power converter in the outlet, which connects to standard AC power wiring. The embedded DC power converter then generates DC power for at least one DC-powered electronic device. A DC power outlet is also provided which may comprise one or more DC power receptacles or DC power cords and plugs, one or more status indicator LEDs, a retraction mechanism for each of the DC power cords, a cooling fan, and an embedded DC power converter. The DC power converters may be universal DC power converters.

Abstract: A power converter capable of providing a range of DC voltages to an external device and a method of providing a range of DC power are provided. The power converter comprises a supply circuit for receiving a request for DC power and for providing the requested DC power. The supply circuit comprises a detection circuit for sensing a connection to an external device, a source controller circuit for determining a DC output power required by the external device, and a converter circuit for generating the required DC output power. The external device comprises a device controller circuit for communicating the request for DC power. A first conductor provides a path for the device to communicate the required DC power to the power converter and for the power converter to supply the required DC power. A second conductor provides a common reference for conducting return current to the power converter.

Abstract: A storage device comprising a magnetic storage medium mounted in a first plane, a read and write mechanism mounted in a second plane that is parallel to the first plane and configured to write information to the magnetic storage medium, and a micromover configured to move the magnetic storage medium in a first direction parallel to the first plane and configured to move the magnetic storage medium in a second direction parallel to the first plane and perpendicular to the first direction.

Abstract: Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.

Abstract: Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.

Abstract: Embodiments of the present invention provide a memory system. In one embodiment, the memory system comprises an array of memory cells, a write circuit configured to write memory cells in the array of memory cells and a control circuit. The control circuit is configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.

Abstract: Embodiments of the present invention provide a memory system. In one embodiment, the memory system comprises an array of memory cells, a write circuit configured to write memory cells in the array of memory cells and a control circuit. The control circuit is configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.

Abstract: Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.