Abstract: This disclosure relates to relatively thin and light weight multilayer textile composites that can provide a high level of protection from the thermal hazards associated with an electrical are flash. The multilayer textile composites comprise a laminate layer stitched with one or more of a laminate or flame retardant textile layer(s).

Abstract: A glove (1) and glove liner (4) is provided, the glove liner (4) comprising a palm portion (11a) and a finger portion (11b); the finger portion (11b) comprising finger sheaths; the liner (4) further comprising a plurality of insulating layers (6,8,10), and the plurality of insulating layers comprising a first insulating layer (6), a second insulating layer (8) and a third insulating layer (10), wherein the first insulating layer (6) extends substantially across the palm portion (11a) and the finger portion (11b), the second insulating layer (8) extends across at least a part of the finger portion (11b), and the third insulating layer (10) extends across at least a part of at least one finger sheath of the finger portion (11b).

Abstract: Described herein are engineered cells, enzymes, methods of use, and bee bread incorporating engineered cells and enzymes as described herein. In certain aspects, described herein are a bacterium containing therein one or more stably-expressing expression vectors for exogenous expression of one or more recombinant carboxylesterase enzymes or oxalate decarboxylase enzymes, thereby providing the engineered cell an exogenous pathway for hydrolyzing ester bonds or removing a carboxyl group. Engineered cells and recombinant enzymes as described herein can be incorporated into bee bread to be fed to a member of the Apidae family of bees or of the Apis or Bombus genus. In additional aspects, such bacteria can also be selected and amplified from the milieu of the hive microorganisms and in some cases they can be molecularly bred to enhance their metabolic capabilities without genetic engineering.

Abstract: A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state tables. A self-contained service of the plurality of self-contained services is randomly and atomically executable. The self-contained service of the plurality of self-contained services changes responsive to the IC design protocol changing. The protocol checking engine checks and validates completeness and correctness of the self-contained service of the reference specification.

Abstract: A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an IC design based upon coverage-based clustering of RTL modules in the design. First, coverage data for code coverage by a plurality of RTL modules in the IC design are collected and a plurality of clusters of related RTL modules of the IC design are generated based on statistical analysis of the collected coverage data and hierarchal information of the RTL modules. When changes are made to the RTL modules during the IC design process, a plurality of affected RTL modules are identified based on the clusters of the RTL modules and a plurality of regression tests are generated dynamically for these affected RTL modules based on their corresponding coverage data. The dynamically generated regression tests are then run to verify the changes made in the IC design.

Abstract: An OR table disposable cover includes a sheet, fluid absorbent on a top side, and fluid impermeable on an opposite, bottom side; a angled support wedge positioned in a head support region on the top side of the sheet; and a soft foam ring member on a top of the angled support which in concert with its underlying support wedge maintains a patient's head in a sniff position. Also provided is a barrier cover having a patient head support member adjacent one end, said head support member being canted at an about 15° angle to the cover, and an operating table carriage that interfaces with the patient either directly, or through a cushion that allows the patient's head to translate along an Y axis of the rail.

Abstract: A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an IC design based upon coverage-based clustering of RTL modules in the design. First, coverage data for code coverage by a plurality of RTL modules in the IC design are collected and a plurality of clusters of related RTL modules of the IC design are generated based on statistical analysis of the collected coverage data and hierarchal information of the RTL modules. When changes are made to the RTL modules during the IC design process, a plurality of affected RTL modules are identified based on the clusters of the RTL modules and a plurality of regression tests are generated dynamically for these affected RTL modules based on their corresponding coverage data. The dynamically generated regression tests are then run to verify the changes made in the IC design.

Abstract: An apparatus for supporting the head and neck for airway management and to facilitate the maintenance of a patent airway under anesthesia, for unconscious patients, and for any circumstance requiring a patent airway while the patient is lying on her side. The apparatus includes a head supporting surface, an adjustable neck supporting surface, and two adjustable jaw support arms to protrude the jaw forward and maintain ventilation while the patient is lying on either of his/her sides.

Abstract: A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state tables. A self-contained service of the plurality of self-contained services is randomly and atomically executable. The self-contained service of the plurality of self-contained services changes responsive to the IC design protocol changing. The protocol checking engine checks and validates completeness and correctness of the self-contained service of the reference specification.

Abstract: An apparatus for supporting the head and neck for airway management and to facilitate the maintenance of a patent airway under anesthesia, for unconscious patients, and for any circumstance requiring a patent airway while the patient is lying on her side. The apparatus includes a head supporting surface, an adjustable neck supporting surface, and two adjustable jaw support arms to protrude the jaw forward and maintain ventilation while the patient is lying on either of his/her sides.

Abstract: A new approach is proposed that contemplates a system and method to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited to, coverage points, protocol transitions, and/or transaction coverage. The automatically generated functional coverage is then verified via formal verification and simulated at the register-transfer level (RTL) during the coverage generation and management process. The coverage data from the formal verification and the simulation runs are then analyzed and used to guide and revise the IC design protocol in a coverage-based closed-loop IC design process.

Abstract: A new approach is proposed that contemplates systems and methods to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited to, coverage points, protocol transitions, and/or transaction coverage. The automatically generated functional coverage is then verified via formal verification and simulated at the register-transfer level (RTL) during the coverage generation and management process. The coverage data from the formal verification and the simulation runs are then analyzed and used to guide and revise the IC design protocol in a coverage-based closed-loop IC design process.

Abstract: A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended state table-based specifications and the templates in all phases in the design flow, resulting in a tight revision loop of debug, verification, and validation across the phases of the design flow.

Abstract: A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended state table-based specifications and the templates in all phases in the design flow, resulting in a tight revision loop of debug, verification, and validation across the phases of the design flow.

Abstract: A sensing assemblage (1) for capturing a transit time, phase, or frequency of energy waves propagating through a medium is disclosed to measure a parameter of the muscular-skeletal system. The sensing assemblage (1) comprises a transducer (2) and a waveguide (3). The transducer (2) is coupled to the waveguide (3) at a first location. A second transducer (11) can be coupled to the waveguide (3) at a second location. An interface material that is transmissive to acoustic energy waves can be placed between transducers (402, 404) and a waveguide (414) to improve transfer. The interface material (408, 410) can affix the transducers (402, 404) to the waveguide (414). Alternatively, a reflecting feature (5) can be placed at a second location of the waveguide (3) to reflect acoustic waves back to the transducer (2) where transducer (2) emits energy waves into the medium and detects propagated energy waves.

Abstract: A load sensing platform (121) is disclosed for capturing a transit time, phase, or frequency of energy waves propagating through a medium that measures a parameter of the muscular-skeletal system. The load sensing platform (121) comprises a sensing assemblage (1), substrates (702, 704, and 706), springs (315), spring posts (708), and spring retainers (710). The sensing assemblage (1) comprises a stack of a transducer (5), waveguide (3), and transducer (6). A parameter is applied to the contact surfaces (8) of the load sensing platform (121). The sensing assemblage (1) measures changes in dimension due to the parameter. Position of the applied parameter can be measured by using more than one sensing assemblage (1). The springs (315) couple to the substrates (702, 704) providing mechanical support and to prevent cantilevering. The spring posts (708) and spring retainers (710) maintain the springs (315) at predetermined locations in the load sensing platform (121).

Abstract: A stem cell expression cassette, comprising a nucleic acid comprising a pluripotent stem cell specific promoter, and a tag sequence, wherein the pluripotent stem cell specific promoter and tag sequences are operatively linked, is provided. Also provided are methods of identifying and methods of selecting a pluripotent cell, using the stem cell expression cassette.

Abstract: A sensing insert device (100) is disclosed for measuring a parameter of the muscular-skeletal system. The sensing insert device (100) can be temporary or permanent. Used intra-operatively, the sensing insert device (100) comprises an insert dock (202) and a sensing module (200). The sensing module (200) is a self-contained encapsulated measurement device having at least one contacting surface that couples to the muscular-skeletal system. The insert dock (202) is a passive component made for different prosthetic component manufacturers as well as for different size prosthetic components. The sensing module (200) fits in an opening or cavity of the insert dock (202). The intra-operative insert device is substantially equal in dimension to an implanted final insert. The sensing insert device (100) is also a permanent prosthetic component. The sensing module (200) residing within the sensing insert device and coupling to a bearing surface of the insert.