Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector using conductive epoxy. The method may comprise: forming thermal isolation trenches 22 and bias contact vias 23 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing conductive epoxy 50 into the bias contact vias 23; replanarizing; depositing a common electrode layer 31 over the thermal isolation trenches 22 and vias 23; depositing an optical coating 26 above the common electrode layer 31; mechanically polishing a backside of the substrate 20 to expose the trench filler 24 and conductive epoxy 50; depositing a contact metal 34 on the backside of the substrate 20; etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20.

Abstract: An infrared sensing array 46 is coupled to a sensing integrated circuit structure 48, and then inter-pixel thermal isolation slots 62 are etched in the optical coating 32 of the infrared sensing array 46. An optional protective material 64 may be deposited over at least the sensing integrated circuit structure 48 for additional protection.

Abstract: A thermal detection system (10) includes a focal plane array (12), a thermal isolation structure (14), and an integrated circuit substrate (16). Focal plane array (12) includes thermal sensors (28), each having an associated thermal sensitive element (30). Thermal sensitive element (30) is coupled with one side to infrared absorber and common electrode assembly (36) and on the opposite side to an associated contact pad (20) disposed on the integrated circuit substrate (16). Reticulation kerfs (52a, 52b) separate adjacent thermal sensitive elements (30a, 30b, 30c) by a distance at least half the average width (44, 46) of a single thermal sensitive element (30a, 30b, 30c). A continuous, non-reticulated optical coating (38) may be disposed over thermal sensitive elements (30a, 30b, 30c) to maximize absorption of thermal radiation incident to focal plane array (12).

Abstract: An etching process is provided using electromagnetic radiation and a selected etchant (52) to selectively remove various types of materials (53) from a substrate (48). Contacts (49, 56, 64) may be formed to shield the masked regions (51) of the substrate (48) having an attached coating (20) during irradiation of the unmasked regions (53) of the substrate (48). The unmasked regions (53) are then exposed to an etchant (52) and irradiated to substantially increase their reactivity with the etchant (52) such that the etchant (52) etches the unmasked regions (53) substantially faster than the masked regions (51) and the contacts (49, 56, 64).

Abstract: A novel multiple level mask (e.g. tri-level mask 36) process for masking achieves a desired thick mask with substantially vertical walls and thus improves the ion milling process of ceramic materials (e.g. BST). An embodiment of the present invention is a microelectronic structure comprising a ceramic substrate, an ion mill mask layer (e.g. photoresist 42) overlaying the substrate, a dry-etch-selective mask layer (e.g. TiW 40) overlaying the ion mill mask layer, the dry-etch-selective mask layer comprising a different material than the ion mill mask layer, a top photosensitive layer (38) overlaying the dry-etch-selective mask layer, the top photosensitive layer comprising a different material than the dry-etch-selective mask layer, and a predetermined pattern formed in the top photosensitive layer, the dry-etch-selective mask layer and the ion mill mask layer. The predetermined pattern has substantially vertical walls in the ion mill mask layer.

Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 and contact vias 23 in a substrate 20; depositing a bias contact metal 32 into the vias 23 forming biasing contact areas around a periphery of the substrate 20; depositing a first trench filler 24 in the trenches 22 and vias 23; replanarizing; depositing a common electrode layer 25 over the thermal isolation trenches and the biasing contact areas; mechanically thinning the substrate 20 to expose the biasing contact area 32 and the trench filler 24; depositing a contact metal 34 on the backside of the substrate 20, the exposed trench filler 24 and the exposed bias contact area; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. The thermal isolation trenches 22 and the bias contact vias 23 may be formed by ion milling or laser vaporization.

Abstract: A system for infrared sensing has thermally sensitive picture elements within a substrate; bias contact areas within the substrate and around a periphery of the thermally sensitive picture elements; a common electrode on a front side of the thermally sensitive picture elements and the bias contact areas; an optical coating on top of the common electrode; a first electrical contact metal on a backside of the thermally sensitive picture elements; and a second electrical contact metal connected to the bias contact areas on a backside of the bias contact areas and electrically connected to the common electrode. The bias contact areas may include a conductive substrate area. In addition, the device may be connected to an integrated circuit by an ohmic connection to the first and/or the second electrical contact metal.

Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector using conductive epoxy. The method may comprise: forming thermal isolation trenches 22 and bias contact vias 23 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing conductive epoxy 50 into the bias contact vias 23; replanarizing; depositing a common electrode layer 31 over the thermal isolation trenches 22 and vias 23; depositing an optical coating 26 above the common electrode layer 31; mechanically polishing a backside of the substrate 20 to expose the trench filler 24 and conductive epoxy 50; depositing a contact metal 34 on the backside of the substrate 20; etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20.

Abstract: This is a system and method of etching pyroelectric devices post ion milling. The method may comprise: forming a mask 32 for thermal isolation trenches on a substrate 14; ion milling thermal isolation trenches 40 in the substrate 14; and etching undesired defects 44 caused by the ion milling by applying a dry etch, a solvent etch, or a liquid etch to the trenches. The etch may include: hydrofluoric acid, perchloric acid, a solution of a chlorine salt and water which is then exposed to ultraviolet light or any similar chemical solution giving the correct reducing properties. The mask 32 and ion milling may be applied from either the front side or the back side of the infrared detector.

Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 20) which are fabricated from novel materials using unique methods of patterning. Trenches (22) are formed in the ceramic substrate from the front side and filled with a filler material (e.g. parylene 24). An elevation layer (e.g. polyimide 26) is deposited above the filler material, and a front side optical coating (e.g. transparent metal layer 34, transparent organic layer 36 and conductive metallic layer 38 ) is elevated above the substrate between the ceramic islands. The elevation layer provides added protection to the optical coating during filler material removal. The substrate is thinned from the back side down through a portion of the trench filler material. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 62) containing a massive array of sensing circuits.

Abstract: A novel method etching through a substrate (e.g. BST 22) comprises removi A n5 Vthick substrate material from the backside of the substrate to form vias (e.g. cavity 24) all the way to the back surface of a frontside thin film (e.g. optical coating 20). To prevent damage to the frontside thin film while etching from the backside of the supporting substrate, the periphery of each frontside pixel is surrounded by a trench (e.g. etch stop trench 30) much deeper than the thickness of the thin film but also significantly shallower than the thickness of the substrate. This trench is then filled with an etch stop material (e.g. photoresist 32). This etch stop may be partially removed by the backside etching method but provides a tolerant means of recognizing when to stop etching before frontside film damage occurs. After etching the substrate down to and partially through the etch stop, the assembly is removed from the substrate etching medium.

Abstract: A bonding apparatus (40) is provided for use in coupling a first substrate (20) with flip chip type interconnections (24) to a second substrate (22) having matching flip chip type interconnections (26). The bonding apparatus (40) includes a pedestal assembly (50) which may be used to align and couple the first substrate (20) with the second substrate (22) and transport the substrates (20 and 22) from the bonding apparatus (40) to a heater assembly (110). Magnetic force is used to maintain the alignment of the first substrate (20) with the second substrate (22) during temperature cycling within the heater assembly. The pedestal assembly (50) includes a magnet slidably disposed on the exterior of the pedestal assembly (50). For some applications, the magnet (60) may be formed from one or more permanent magnets. For other applications, magnet (60) may be formed from one or more electromagnets.

Abstract: A thermal detection system (10) includes a focal plane array (12), a thermal isolation structure (14), and an integrated circuit substrate (16). Focal plane array (12) includes thermal sensors (28), each having an associated thermal sensitive element (30). Thermal sensitive element (30) is coupled with one side to infrared absorber and common electrode assembly (36) and on the opposite side to an associated contact pad (20) disposed on the integrated circuit substrate (16). Reticulation kerfs (52a, 52b) separate adjacent thermal sensitive elements (30a, 30b, 30c) by a distance at least half the average width (44, 46) of a single thermal sensitive element (30a, 30b, 30c). A continuous, non-reticulated optical coating (38) may be disposed over thermal sensitive elements (30a, 30b, 30c) to maximize absorption of thermal radiation incident to focal plane array (12).

Abstract: In an exemplary thermal imaging system (20, 120, 220 and 320), a thermal isolation structure (50 and 150) is disposed on an integrated circuit substrate (70 and 170) for electrically connecting and mechanically bonding a focal plane array (30 and 230) of thermal sensors (40 and 240). Each mesa-type structure (52, 54 and 152) includes at least one mesa conductor (56, 58, 156 and 158) that extends from the top of the mesa-type structure (52, 54 and 152) to an adjacent contact pad (72 and 74). The mesa conductors (56, 58, 156 and 158) provide both biasing voltage (V.sub.B) for the respective thermal sensor (40 and 240) and a signal flow path (V.sub.S) for the respective thermal sensor (40 and 240). The mesa conductors (56, 56, 156 and 158) may be used to provide biasing voltage (V.sub.B) to either a single ferroelectric element (242) or a pair of ferroelectric elements (42 and 44).

Abstract: In an exemplary thermal imaging system (20, 120, 220 and 320), a thermal isolation structure (50 and 150) is disposed on an integrated circuit substrate (70 and 170) for electrically connecting and mechanically bonding a corresponding focal plane array (30, 130, and 230) of thermal sensors (40, 140, and 240). Each mesa-type structure (52, 54 and 152) includes at least one mesa conductor (56, 58, 156 and 158) that extends from the top of the mesa-type structure (52, 54 and 152) to an adjacent contact pad (72 and 74). The mesa conductors (56, 58, 156 and 158) provide both biasing voltage (V.sub.B) for the respective thermal sensor (40 and 240) and a signal flowpath (V.sub.s) for the respective thermal sensor (40 and 240). The mesa conductors (56, 58, 156 and 158) may be used to provide biasing voltage (V.sub.B) to either a single ferroelectric element (242 and 243) having a void space (277 and 279) or a pair of ferroelectric elements (42 and 44).

Abstract: A thermal detection system (100, 200) includes a focal plane array (102, 202), a thermal isolation structure (104, 204) and an integrated circuit substrate (106, 206). The focal plane array (102, 202) includes thermal sensors (114, 214) formed from a pyroelectric element (116, 216), such as barium strontium titanate (BST). One side of the pyroelectric element (116, 216) is coupled to a contact pad (110, 210) disposed on the integrated circuit substrate (106, 206) through a mesa strip conductor (112, 212) of the thermal isolation structure (104, 204). The other side of the pyroelectric element (116, 216) is coupled to a common electrode (120, 220). In one embodiment, slots (128) are formed in the common electrode (120) intermediate the thermal sensors (114) to improve inter-pixel thermal isolation. In another embodiment, slots (236) are formed in the optical coating (224) to improve inter-pixel thermal isolation.

Abstract: A bonding apparatus (40) is provided for use in coupling a first substrate (20) with flip chip type interconnections (24) to a second substrate (22) having matching flip chip type interconnections (26). The bonding apparatus (40) includes a pedestal assembly (50) which may be used to align and couple the first substrate (20) with the second substrate (22) and transport the substrates (20 and 22) from the bonding apparatus (40) to a heater assembly (110). Magnetic force is used to maintain the alignment of the first substrate (20) with the second substrate (22) during temperature cycling within the heater assembly. The pedestal assembly (50) includes a magnet slidably disposed on the exterior of the pedestal assembly (50). For some applications, the magnet (60) may be formed from one or more permanent magnets. For other applications, magnet (60) may be formed from one or more electromagnets.

Abstract: A bonding apparatus (40) having one or more electromagnets (60) is provided for use in coupling a first substrate (20) with flip chip type interconnections (24) to a second substrate (22) having matching flip chip type interconnections (26). The bonding apparatus (40) includes a pedestal assembly (50) which may be used to align and couple the first substrate (20) with the second substrate (22). The bonding apparatus (40) includes an electrical control system (108) with a control unit (130) for varying the amount of electrical power supplied to the electromagnet (60). One or more heater assemblies (110) are provided for temperature cycling of the substrates (20 and 22) during the bonding process. Magnetic force is used to maintain the alignment of the first substrate (20) with the second substrate (22) during temperature cycling.