Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: A method for carrier aggregation receives a signal with multiple non-contiguous carrier bands. Frequency converting of the signal to a compressed single intermediate frequency band with a pseudonoise code applied to a local oscillation of each of the multiple non-contiguous carrier bands while maintaining separation of the multiple non-contiguous carrier bands permits reduced complexity digital signal processing to detect spectral power density and demodulate waveforms across multiple channels. A receiver includes a pseudorandom noise generator applying a pseudo noise code to the local oscillator generator to produce a unique set of spectral tones in the output signal that sample-specific channels over the multiple non-contiguous carrier bands.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, and a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. First chiplets have a first thickness and backsides bonded directly to first portions of the areas of the top surface of the backside capping layer. Second chiplets have a second, thinner thickness and backsides bonded to second portions of the areas of the top surface of the backside capping layer. The backside of the second chiplets are directly bonded to metal backfill plugs of at second portions of the backside capping layer. A lateral bonding material bonds side surfaces of the first chiplets, the second chiplets and the plugs to side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: A predistorter for an electro-optical converter includes a plurality of low noise RF amplifiers distributed along a transmission line that receive an RF input. Second order intermodulation injection (IM2) circuitry includes an inductively-degenerated frequency doubler to square and filter IM2 products of the RF input. A Mach-Zehnder Modulator (MZM) is used for electro-optical conversion. Feed forward circuitry injects IM2 to independently propagate RF intermodulation components with velocity matching to the MZM. At least one driver injects the RF input and RF intermodulation components into the MZM.

Abstract: A passive, tunable on-chip load modulation network for a high-efficiency power amplifier includes a ring transmission line. An output is connected to a first point on the ring transmission line. A first switched input is connected to a second point on the ring transmission line, the second point being located on the ring transmission line to provide a first impedance transformation. A second switched input is connected to a third point on the ring transmission line, the third point being located to provide a second impedance transformation that is unique from the first impedance transformation.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: Methods and apparatus for implementing a power efficient amplifier device through the use of a main (primary) and auxiliary (secondary) power amplifier are described. The primary and secondary amplifiers operate as current sources providing current to the load. Capacitance coupling is used to couple the primary and secondary amplifier outputs. In some embodiments the combination of primary and secondary amplifiers achieve high average efficiency over the operating range of the device in which the primary and secondary amplifiers are used in combination as an amplifier device. The amplifier device is well suited for implementation using CMOS technology, e.g., N-MOSFETs, and can be implemented in an integrated circuit space efficient manner that is well suited for supporting RF transmissions in the GHz frequency range, e.g., 30 GHz frequency range. The primary amplifier in some embodiments is a CLASS-AB or B amplifier and the secondary amplifier is a CLASS-C amplifier.

Abstract: A method for carrier aggregation receives a signal with multiple non-contiguous carrier bands. Frequency converting of the signal to a compressed single intermediate frequency band with a pseudonoise code applied to a local oscillation of each of the multiple non-contiguous carrier bands while maintaining separation of the multiple non-contiguous carrier bands permits reduced complexity digital signal processing to detect spectral power density and demodulate waveforms across multiple channels A receiver includes a pseudorandom noise generator applying a pseudo noise code to the local oscillator generator to produce a unique set of spectral tones in the output signal that sample-specific channels over the multiple non-contiguous carrier bands.

Abstract: A method for switching interval modulation includes modulating an RF input data signal while generating and inserting additional pulses in transitions of the data signal. The additional pulses are structured to shift transition noise into higher order harmonics. Higher order harmonics are easily filtered. The generating is conducted in the digital domain. The additional pulses can be used to simplify the transmit chain through optical modulators and improve the signal integrity over long distances, can be applied at the output of a transmitter to filter power amplifier distortion, and can be appplied to non-linear RF over fiber for a distributed MIMO system.

Abstract: A predistorter for an electro-optical converter includes a plurality of low noise RF amplifiers distributed along a transmission line that receive an RF input. Second order intermodulation injection (IM2) circuitry includes an inductively-degenerated frequency doubler to square and filter IM2 products of the RF input. A Mach-Zehnder Modulator (MZM) is used for electro-optical conversion. Feed forward circuitry injects IM2 to independently propagate RF intermodulation components with velocity matching to the MZM. At least one driver injects the RF input and RF intermodulation components into the MZM.

Abstract: Methods and apparatus for implementing a power efficient amplifier device through the use of a main (primary) and auxiliary (secondary) power amplifier are described. The primary and secondary amplifiers operate as current sources providing current to the load. Capacitance coupling is used to couple the primary and secondary amplifier outputs. In some embodiments the combination of primary and secondary amplifiers achieve high average efficiency over the operating range of the device in which the primary and secondary amplifiers are used in combination as an amplifier device. The amplifier device is well suited for implementation using CMOS technology, e.g., N-MOSFETs, and can be implemented in an integrated circuit space efficient manner that is well suited for supporting RF transmissions in the GHz frequency range, e.g., 30 GHz frequency range. The primary amplifier in some embodiments is a CLASS-AB or B amplifier and the secondary amplifier is a CLASS-C amplifier.

Abstract: A circuit topology including stacked power amplifiers (e.g., class D PA cells) in a ladder arranged in a house-of-cards topology such that the number of stacked-domains follows a decaying triangular series N, N?1, N?2, . . . , N?i from a fixed ladder to an ith ladder to provide a 1:(i+1) voltage conversion ratio, each stacked domain outputs its power via a flying domain power amplifier cell, and each ladder balances stacked domains of a prior ladder and combines power from all prior ladders.

Abstract: A circuit topology including stacked power amplifiers (e.g., class D PA cells) in a ladder arranged in a house-of-cards topology such that the number of stacked-domains follows a decaying triangular series N, N?1, N?2, . . . , N?i from a fixed ladder to an ith ladder to provide a 1:(i+1) voltage conversion ratio, each stacked domain outputs its power via a flying domain power amplifier cell, and each ladder balances stacked domains of a prior ladder and combines power from all prior ladders.

Abstract: In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.

Abstract: In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.