Abstract: A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias.

Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias.

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract: A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias.

Abstract: Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6 keV, and at a relatively low implant energy, e.g., about 1.5 to about 2E15/cm2.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract: An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region.

Abstract: A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract: MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.

Abstract: The present invention is directed to a diode with an asymmetric silicon germanium anode and methods of making same. In one illustrative embodiment, the diode includes an anode comprising a P-doped silicon germanium material formed in a semiconducting substrate, an N-doped silicon cathode formed in the semiconducting substrate, a first conductive contact that is conductively coupled to the anode and a second conductive contact that is conductively coupled to the cathode.

Abstract: A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias.

Abstract: A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6 keV, and at a relatively low implant energy, e.g., about 1.5 to about 2E15/cm2.