Patents by Inventor James F. Friend

James F. Friend has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6886107
    Abstract: A system and method for configuring a control plane within a network device. One of a pair of control processors is selected to act as the master of the control plane and the other control processor is specified as a standby control processor in normal operation. In the case of a failover or switchover event, the standby control processor assumes the role of the master of the control plane and updates configuration information within line cards in the network device as necessary. A state machine within the control processor is employed to manage state transitions for the control processor. Each control processor generates at least one signal that indicates whether it is capable of serving as the master of the control plane. Master selection logic selects one of the control processors as the master for the control plane and in one embodiment advertises the identification of the master control processor via triply redundant signals.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: April 26, 2005
    Assignee: Marconi Intellectual Property (Ringfence), Inc.
    Inventors: Robert J. Walsh, Steve N. Barbas, James F. Friend
  • Publication number: 20020099972
    Abstract: A system and method for configuring a control plane within a network device. One of a pair of control processors is selected to act as the master of the control plane and the other control processor is specified as a standby control processor in normal operation. In the case of a failover or switchover event, the standby control processor assumes the role of the master of the control plane and updates configuration information within line cards in the network device as necessary. A state machine within the control processor is employed to manage state transitions for the control processor. Each control processor generates at least one signal that indicates whether it is capable of serving as the master of the control plane. Master selection logic selects one of the control processors as the master for the control plane and in one embodiment advertises the identification of the master control processor via triply redundant signals.
    Type: Application
    Filed: November 15, 2001
    Publication date: July 25, 2002
    Applicant: Crescent Networks, Inc.
    Inventors: Robert J. Walsh, Steve N. Barbas, James F. Friend