Abstract: A high-power-factor power supply has a full-wave rectifier for rectifying an AC line voltage, a power regulator including switch means responsive to a control signal for controlling the application of the rectifier output to a load; and a control circuit for producing a switching control signal. The control signal includes a pair of AC line detectors: a first connected in a closed-loop automatic gain control arrangement, and the other connected in an open-loop arrangement. The control circuit initially produces a CURRENT DEMAND REFERENCE signal that is directly related to the difference between the power supply DC output voltage and a self-generated constant reference, and to the waveform shape of the AC line voltage, and is inversely related to magnitude changes of the AC line voltage. The control signal then produces the switching control signal in response to both the CURRENT DEMAND REFERENCE signal and the current flowing in the power supply.

Abstract: In one N-type epitaxial pocket of an integrated circuit there is formed a vertical NPN transistor and two other P-type regions each positioned adjacent but spaced from the P-type base region of the NPN. A metal gate over the gap between the base and one of the other P-type regions forms a high input-impedance P-MOS stage driving the NPN. A metal layer contacts both the NPN emitter and the PNP emitter formed by the third P-type region. This PNP transistor clamps the NPN collector-emitter to a safe voltage when switching an inductive load, and in a particularly efficient manner. A second P-MOS transistor is formed by extending the metal layer over the gap between the NPN-base and the third P-type region which transistor is capable of preventing leakage current out of the input P-MOS transistor in the off state form turning on the NPN transistor.

Abstract: An integrated circuit having first and second N-type epitaxial layers grown over a P-type silicon substrate includes PN junction isolated pockets. In at least one pocket is a small signal device, namely an I.sup.2 L transistor. In an adjacent pocket is a vertical NPN power transistor wherein the base is a P-type buried layer extending upward out of an N-type buried layer, both of which are grown from the substrate surface. The upward diffusion of the base region is substantially terminated at the interface between the epitaxial layers and thus the base width and charge are precisely controllable. Connected in the up-beta power transistor mode, the gain is precisely controllable independent of process variations made to control small signal devices. In the down-beta mode and connected as a diode with base and collector shorted, an excellent clamp diode is made producing an unusually low parasite current in the substrate.

Abstract: A test circuit, including a vertical NPN, a lateral PNP and a vertical PNP transistor plus a diffused resistor and a thin film resistor, is formed by altogether simultaneous steps with corresponding components of each principal integrated circuit. Four dedicated test pads in each integrated circuit lead to all bases, collectors, emitters and resistor extremities so as to permit substantially unshunted measurements of all basic transistor and resistor electrical parameters.

Abstract: An integrated circuit has a P-type substrate and two N-type epitaxial layers. P-type isolation walls define pockets in the dual-layer epitaxial material, a power transistor being formed in one and an inverted I.sup.2 L transistor being formed in another of the pockets. An upper buried layer doped with antimony (N-type) at the interface between the two epitaxial layers extends into the outer epitaxial layer forming a N.sup.+ N holes-barrier junction. This junction is spaced from the depletion region of the normally forward biased base emitter junction by from 0.1 to 0.45 holes-diffusion lengths to provide high emitter efficiency in 0.5 to 5 ohm-cm epitaxial material. The P-type bases of the two kinds of transistors have the same depth but the N-type emitter of the power transistor is shallower than the N-type collector of the inverted transistor although formed earlier. Breakdown voltage of the power transistor is thus enhanced while the base width of the I.sup.