Abstract: Systems and methods for obtaining access to database files m a computing system. A method may include receiving a first call from a database management system requesting access to a database file. The method may further include transmitting a second call to an operating system interface requesting that a memory-mapped data expanse file be created. The method may also include receiving a first address representing the database file in response to successful mapping of the database file to the memory-mapped data expanse file located at the operating system interface.

Abstract: Systems and methods for obtaining access to database files in a computing system. A method may include receiving a first call from a database management system requesting access to a database file. The method may further include transmitting a second call to an operating system interface requesting that a memory-mapped data expanse file be created. The method may also include receiving a first address representing the database file in response to successful mapping of the database file to the memory-mapped data expanse file located at the operating system interface.

Abstract: Systems and methods for obtaining access to database files in a computing system. A method may include receiving a first call from a database management system requesting access to a database file. The method may further include transmitting a second call to an operating system interface requesting that a memory-mapped data expanse file be created. The method may also include receiving a first address representing the database file in response to successful mapping of the database file to the memory-mapped data expanse file located at the operating system interface.

Abstract: Systems and methods for event logging in a just-in-time static translation system are disclosed. One method includes executing a workload in a computing system having a native instruction set architecture, the workload stored in one or more banks of non-native instructions. At least a portion of the workload is further included in one or more banks of native instructions and executing the workload comprises executing at least part of the workload from the one or more banks of native instructions. The method also includes determining an amount of time during execution of the workload in which the execution of the workload occurs from the one or more banks of native instructions. The method includes generating a log including performance statistics generated during execution of the workload, the performance statistics including the amount of time.

Abstract: Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.

Abstract: A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit.

Abstract: Approaches for emulating an operating system. A method includes executing a first operating system (OS) on an instruction processor. The first OS includes instructions of a first instruction set that are native to the instruction processor. A second OS is emulated on the first OS and includes instructions of a second instruction set that are not native to the instruction processor. An emulated transfer-of-control instruction is determined during emulation of the second OS to target either instructions of the first set or the second set. In response to determining that instructions of the first set are targeted, control is transferred to the targeted instructions of the first set on the instruction processor. In response to determining that instructions of the second set are targeted, the targeted instructions of the second set are retrieved and emulated.

Abstract: Approaches for dispatching routines in an emulated operating system. A method includes executing a first operating system (OS) on an instruction processor of a data processing system. The first OS includes instructions of a first instruction set that are native to the instruction processor. A second OS is emulated on the first OS and includes instructions of a second instruction set that are not native to the instruction processor. A first plurality of tasks is created by the emulated second OS. The first OS individually schedules the first plurality of tasks and dispatches the first plurality of emulated tasks for emulation according to the scheduling.

Abstract: This invention provides to large-scale operating systems supporting multiple classes of tasks a method to allocate processor resources to the classes according to a probability model. It is useful in preventing a class from being denied resources by giving it positive measure in the model. A first stage probability algorithm assigns classes of tasks to an IP resource available to a given scheduler queue. Each class is allocated a probability level in a lottery-type draw in this first stage. In preferred embodiments, a second stage probability algorithm is used to assign tasks within a class to an available processor resource. This second stage algorithm is biased in a feedback manner by task resource usage history. Tasks of extreme high or low priority may avoid the probabilistic mechanisms in preferred embodiments.

Abstract: An Operating System (OS) function maps affinity to processors for each new task and except for certain circumstances where other processors are permitted to steal tasks, this affinity remains unchanged. Hierarchical load balancing is mapped through an affinity matrix (that can be expressed as a table) which is accessed by executable code available through a dispatcher to the multiplicity of instruction processors (IPs) in a multiprocessor computer system. Since the computer system has multiple layers of cache memories, connected by busses, and crossbars to the main memory, the hierarchy mapping matches the cache memories to assign tasks first to IPs most likely to share the same cache memory residue from related tasks, or at least less likely to incur a large access time cost. Each IP has its own switching queue (SQ) for primary task assignments through which the OS makes the initial affinity assignment.