Abstract: Boundary Scan integrated circuits are provided with a plurality of new registers between two dedicated pins, Test Data In (TDI) and Test Data Out (TDO) pins. The new registers include an address register and a plurality of test data registers which are addressable by the address register using address-dependent instructions in the instruction register (IR). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instruction placed in the instruction register followed by an address-dependent instruction. The ADDLOAD instruction makes the address register active between the TDI and TDO pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address-dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. At the same time non-addressable registers, such as the Boundary Scan register, use address-independent instructions.

Abstract: A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.

Abstract: Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state.

Abstract: The invention is concerned with pneumatic apparatus for removing fibers, dust and threads from industrial processes, particularly in the textile industry. In an arrangement in which there is a plurality of collecting heads each associated with a part of a machine from which dust, fibers or threads are likely to be emitted, each of these collectors leads into a common duct which in turn leads to a suction fan and filter.The suction pressure (or any other physical characteristic of the air in the duct which relates to the suction pressure) is detected, and a signal from this detector is compared with a signal corresponding to a desired suction pressure and the output signal from the comparator used to control the speed of the driving motor for the suction fan.

Abstract: The invention is concerned with pneumatic apparatus for removing fibres, dust and threads from industrial processes, particularly in the textile industry. In an arrangement in which there is a plurality of collecting heads each associated with a part of a machine from which dust, fibres or threads are likely to be emitted, each of these collectors leads into a common duct which in turn leads to a suction fan and filter.The suction pressure (or any other physical characteristic of the air in the duct which relates to the suction pressure) is detected, and a signal from this detector is compared with a signal corresponding to a desired suction pressure and the output signal from the comparator used to control the speed of the driving motor for the suction fan.