Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: A memory device includes a memory array having memory cells associated with wordlines. Control logic, operatively coupled with the memory array, causes a first set of memory cells, associated with a first wordline of the memory array, to be programmed with a first set of threshold voltage distributions. After a second set of memory cells, associated with a second wordline that is adjacent to the first wordline, has been programmed, the control logic causes the first set of memory cells to be further coarse programmed with an intermediate third set of threshold voltage distributions that is greater in number than the first set of threshold voltage distributions. The control logic causes the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions.

Abstract: A set of data items programmed to a first region of a memory subsystem according to a first sequence is identified. The first sequence does not correspond to a target sequence. The set of data items is copied from the first region to a second region of the memory subsystem according to the target sequence.

Abstract: An example memory device includes a memory array and processing logic, operatively coupled with the memory array. The processing logic is configured to perform operations, including: identifying a set of sample voltages associated with a chosen read level; obtaining, for each sample voltage of the set of sample voltages, a cell count corresponding to a number of target cells of the memory array that have a threshold voltage lower than the sample voltage; and determining, based on the cell count, a calibrated read level associated with a state information bin to which the target cells are assigned.

Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

Abstract: Some embodiments relate to a method of energy management for an electrical system of a building. The electrical system comprises one or more inflexible energy assets and one or more flexible energy assets. The method comprises: obtaining power data for the electrical system; and operating the one or more flexible energy assets to balance electrical power in the electrical system by: determining an energy forecast for the electrical system based on the power data, wherein the energy forecast is determined using a forecasting model for the electrical system; and determining a power schedule for controlling the one or more flexible energy assets to balance the electrical power in the electrical system using the determined energy forecast.

Abstract: A set of data items programmed to a first region of a memory subsystem is identified. The set of data items is programmed to the first region according to an initial sequence. A determination is made of whether the initial sequence corresponds to a target sequence associated with accessing the set of data items. Responsive to a determination that the initial sequence does not correspond to the target sequence, the set of data items is copied from the first region to a second region of the memory subsystem according to the target sequence.

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Abstract: Host data to be programmed to a plurality of memory cells associated with a wordline of a memory device is received from a host system. The host data into a plurality of partitions is divided. Each of the plurality of partitions is divided into a respective plurality of sub-partitions. One or more modulation mappings to be applied to the plurality of sub-partitions are determined based on the host data of the plurality of partitions. Host data of each sub-partition of the plurality of sub-partitions is modified based on the one or more modulation mappings. The modified host data of each sub-partition is written to the plurality of memory cells associated with the wordline.

Abstract: Described are systems and methods for adaptable data modulation. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: receiving a unit of data to be written to the memory device; splitting the unit of data into a plurality of segments; modulating each segment of the unit of data by a modulation operation using a modulation mask derived from a corresponding seed value; and generating a modulated unit of data comprising a plurality of modulated segments and a plurality of corresponding seed identifiers, wherein each seed identifier identifies a seed value that has been used for modulating a respective segment of the unit of data.

Abstract: Described are systems and methods for dynamically configurable data modulation in memory systems. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: receiving a unit of data to be stored on the memory device; identifying a set of parameter values characterizing a target location of the unit of data on the memory device; determining a modulation code corresponding to the set of parameter values; modulating the unit of data by a modulation operation identified by the modulation code; and storing, on the memory device, the modulated unit of data.

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Abstract: A memory device includes an array of memory cells associated with a plurality of wordlines and control logic operatively coupled with the array of memory cells. The control logic can receive a program command comprising a digital value indicating that a physical address of the program command corresponds to a retired wordline of the plurality of wordlines. The control logic can generate dummy data in response to detecting the digital value within the program command. The memory logic can cause the dummy data to be programmed to memory cells that are selectively coupled to the retired wordline.