Abstract: Systems and methods for providing image motion artifact correction for a color sequential (CS) display in a display system in a vehicle. The system includes a processor operationally coupled to a source of a coherent RGB image frame, a source of a line of sight (LOS) motion rate, and the display system, the processor configured to, calculate a sub-frame (SF) timing rate for the CS display; unpack the coherent RGB image frame into a Red, a Green, and a Blue frame; calculate a red, a green, and a blue pixel shift, as a function of a LOS rate change; apply the red pixel shift to the Red frame, the green pixel shift to the Green frame, and the blue pixel shift to the Blue frame, thereby creating modified RGB sub-frames; and re-packing the modified RGB sub-frames into a modified coherent RGB image frame for the CS display.

Abstract: Systems and methods for providing image motion artifact correction for a color sequential (CS) display in a display system in a vehicle. The system includes a processor operationally coupled to a source of a coherent RGB image frame, a source of a line of sight (LOS) motion rate, and the display system, the processor configured to, calculate a sub-frame (SF) timing rate for the CS display; unpack the coherent RGB image frame into a Red, a Green, and a Blue frame; calculate a red, a green, and a blue pixel shift, as a function of a LOS rate change; apply the red pixel shift to the Red frame, the green pixel shift to the Green frame, and the blue pixel shift to the Blue frame, thereby creating modified RGB sub-frames; and re-packing the modified RGB sub-frames into a modified coherent RGB image frame for the CS display.

Abstract: One embodiment includes an apparatus for display of video data from a designated number of an N number of video channels. The apparatus comprises an N number of video decoders to receive the video data from the N number of video channels. A designated number of the N number of video decoders to decode the video data from the designated number of the N number of video channels. The apparatus also comprises a P number of video processing pipelines coupled to the N number of video decoders through a switch network. The switch network configured to connect any of the outputs from the N number of video decoders to any of the inputs into the P number of video processing pipelines.