Patents by Inventor James G Champlain
James G Champlain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10192979Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.Type: GrantFiled: July 11, 2016Date of Patent: January 29, 2019Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Jonathan L. Shaw, John Bradley Boos, Kevin Jensen, James G. Champlain, Bradford B. Pate, Byoung-don Kong, Doewon Park, Joan E. Yater
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Publication number: 20170012103Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.Type: ApplicationFiled: July 11, 2016Publication date: January 12, 2017Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Jonathan L. Shaw, John Bradley Boos, Kevin Jensen, James G. Champlain, Bradford B. Pate, Byoung-don Kong, Doewon Park, Joan E. Yater
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Patent number: 9054169Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: GrantFiled: October 2, 2014Date of Patent: June 9, 2015Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Publication number: 20150014745Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: ApplicationFiled: October 2, 2014Publication date: January 15, 2015Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Patent number: 8884265Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: GrantFiled: January 16, 2014Date of Patent: November 11, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Publication number: 20140264278Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: ApplicationFiled: January 16, 2014Publication date: September 18, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Patent number: 8652959Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: February 1, 2013Date of Patent: February 18, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Publication number: 20130149845Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: ApplicationFiled: February 1, 2013Publication date: June 13, 2013Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Patent number: 8461664Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: May 25, 2011Date of Patent: June 11, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A Papanicolaou
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Patent number: 8076700Abstract: This disclosure describes a semiconductor device that can be used as a mixer at RF frequencies extending from a few tens of GHz into the THz frequency range. The device is composed of narrow bandgap semiconductors grown by solid source molecular beam epitaxy. The device can comprise a GaSb substrate, a AlSb layer on the GaSb substrate, a In0.69Al0.31As0.41Sb0.59 layer, on the AlSb layer and wherein the In0.69Al0.31As0.41Sb0.59 comprises varying levels of Te doping, a In0.27Ga0.73Sb layer on the In0.69Al0.31As0.41 Sb0.59 layer, wherein the In0.27Ga0.73Sb layer is Be doped, wherein the first section of the In0.69Al0.31As0.41Sb0.59 layer has is Te doped, wherein the second section of the In0.69Al0.31As0.41Sb0.59 layer has a grade in Te concentration, and wherein the third section of the In0.69Al0.31As0.41Sb0.59 layer is Te doped.Type: GrantFiled: June 2, 2009Date of Patent: December 13, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Richard Magno, Mario Ancona, John Bradley Boos, James G Champlain, Harvey S Newman
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Publication number: 20110297916Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: ApplicationFiled: May 25, 2011Publication date: December 8, 2011Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Publication number: 20090302352Abstract: This disclosure describes a semiconductor device that can be used as a mixer at RF frequencies extending from a few tens of GHz into the THz frequency range. The device is composed of narrow bandgap semiconductors grown by solid source molecular beam epitaxy. The device can comprise a GaSb substrate, a AlSb layer on the GaSb substrate, a In0.69Al0.31As0.41Sb0.59 layer, on the AlSb layer and wherein the In0.69Al0.31As0.41Sb0.59 comprises varying levels of Te doping, a In0.27Ga0.73Sb layer on the In0.69Al0.31As0.41 Sb0.59 layer, wherein the In0.27Ga0.73Sb layer is Be doped, wherein the first section of the In0.69Al0.31As0.41Sb0.59 layer has is Te doped, wherein the second section of the In0.69Al0.31As0.41Sb0.59 layer has a grade in Te concentration, and wherein the third section of the In0.69Al0.31As0.41Sb0.59 layer is Te doped.Type: ApplicationFiled: June 2, 2009Publication date: December 10, 2009Applicant: The Government of the United States of America, as represenied by the Secretary of the NavyInventors: Richard Magno, Mario Ancona, John Bradley Boos, James G. Champlain, Harvey S. Newman