Abstract: A power converter capable of providing a range of DC voltages to an external device and a method of providing a range of DC power are provided. The power converter comprises a supply circuit for receiving a request for DC power and for providing the requested DC power. The supply circuit comprises a detection circuit for sensing a connection to an external device, a source controller circuit for determining a DC output power required by the external device, and a converter circuit for generating the required DC output power. The external device comprises a device controller circuit for communicating the request for DC power. A first conductor provides a path for the device to communicate the required DC power to the power converter and for the power converter to supply the required DC power. A second conductor provides a common reference for conducting return current to the power converter.

Abstract: Peer-to-peer Direct Memory Access (DMA) permits the efficient transfer of data from one DMA capable Application Specific Integrated Circuit (ASIC) block to another without accessing memory. The peer-to-peer transfer can be done over a standard AMBA AHB bus architecture without side band signals and without violating the AHB specification.

Abstract: An interpolation scheme uses cubic subdivision to index a position of an input color value in a color space relative to neighboring vertices. The indexed position of the input color value is expanded and the neighboring vertices are combined together according to the expanded index to generate an output color value.

Abstract: A microprocessor system is provided that includes a first memory bank having a first base address and a second memory bank having a second base address. A memory controller is adapted to register the first and second base addresses. A swap command is adapted to instruct the memory controller to swap the first and second base addresses. A microprocessor issues the swap command. The memory controller includes a first base address register adapted to register the first base address and a second base address register adapted to register the second base address. A command register is adapted to register the swap command. In one embodiment, the first memory bank is a DRAM bank and the second memory bank is a ROM bank. The swap command instructs the memory controller to swap the first and second base addresses before temporary storage is established in the DRAM bank.

Abstract: A color data converter includes a plurality of memories configured to store lattice points for a color space. The lattice points of the first axis are assigned to memories in a sequential manner. The lattice points along the other two axes are assigned to memories in an alternating manner.

Abstract: The invention provides apparatus for the transfer of data/command between a master controller and one or more client controllers. The apparatus in accordance with the invention includes a bi-directional data bus for conveying plural bits of data or command between a master controller and one or more client controllers; direction signal controlling the direction in which data or command bits are conveyed on the data bus as between the master controller and a connected one of the one or more client controllers; a pair of ready signals including a transmit ready signal asserted by a source of data or command bits placed on the data bus and including a receive ready signal asserted by a destination for the data or command bits placed on the data bus; and a clock signal for indicating the presence of valid data or command bits on the data bus on a leading or trailing edge thereof. Preferably, a command/data signal is also provided to indicate the type of information placed on the data bus by the source.

Abstract: A destructive read sense-amp (typically used in SRAM) includes circuitry for disabling its amplifier circuitry in response to a predetermined logic level appearing at its output, circuitry for preserving the predetermined logic level appearing at its output, and circuitry for modifying data carried on data transmission lines connected to its differential inputs. The output preserving means and data modifying circuitry are only enabled while the sense-amp's amplifier circuitry is disabled. In a preferred implementation, the destructive read sense-amp writes a logic "0" into a memory cell upon reading a logic "1" from the same memory cell. The reading and writing of data occurs within a single read cycle.